Sometimes, the best solutions are, indeed, simple

Sometimes, the best solutions are, indeed, simple

My PhD student Pedro Paz Mongil came one day to my office asking me about the calculation of the arcsine and arccosine in a digital circuit. For this type of functions, the CORDIC algorithm is usually the first option to check. And we did.

However, we observed a strange behavior in the calculations, with regions in the domain of the function that showed big errors with respect to the expected calculation. The reason for this behavior is complex, and you better ask Pedro about it... The point is that these errors occur and they are not possible to solve using the conventional CORDIC.

By digging into the literature, we found the so-called double iteration CORDIC that solved the issue by calculating each CORDIC iteration twice. This was a better option, but we were not convinced to use it due to the fact that this doubled the complexity of the design.

So we started to think about the issue and we discovered that the problem was related to the compensation of the gain of one of the factors. Ideally, the calculation should be

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However, calculating the square root in hardware is not feasible with a reduced amount of resources.

The double iteration CORDIC solved it by calculating

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at the expense of doubling the number of iterations.

But then, Pedro realized that the squared term of the first equation can be approximated by

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This is a very good approximation that grants an accuracy of 32 bits, much more than enough for most applications. And, as it involves sums and multiplications by powers of two, it is very cheap in hardware. So, problem solved.

This simple and clever idea gave as a result a journal paper that has been recently published as Open Access as

P. Paz and M. Garrido, "CORDIC-Based Computation of Arcsine and Arccosine Functions on FPGA", Transactions on Circuits and Systems II: Express Briefs, 2023.

In the end, the best solution was also the simplest...

This work has been carried out in the frame of the project "RAFFTING: Realizing Advanced FFT Implementations for 6G", PID2021-126991NA-I00, funded by the Spanish Ministry of Science and Innovation, the AEI, and the European Regional Development Fund through the call "Proyectos de Generación de Conocimiento, 2021".

Pedro Velasco

R&D Project Manager and Technology Advisor

1 年

Congratulations Mario and Pedro. That reminds me quite a lot of the "Quake III Arena fast inverse root square solver" ??

Miguel Bordallo

Associate Professor at 6G Flagship, University of Oulu

1 年

Excellent observation!

Ludvig Vidlid

Algorithms and FPGAs at Truestream

1 年

Woho, PhD work I can understand :D. Very nice!

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