Is the Software a Nightmare for #Xilinx #Versal ACAP?
Finally, Xilinx shipped Versal “The World’s First ACAP” or Adaptive Compute Acceleration Platform.
The important question is: Are the software platforms and algorithms ready for the Versal technology? In other words, how can the software architectures dedicate and divide (not even optimize) the elements of mathematical algorithms between Scaler engines (ARM A72 and ARM R5 cores), Adaptable engine (FPGA) and Intelligent engines (AI and DSP engines) inside Versal ACAP.
Is the high-speed interconnect NOC (Network On Chip) efficient enough for low latency, high bandwidth data transferring between the enginess?
We know that the parallel/manycore processing experienced the same issues. Still a lot of applications that are running in parallel/manycore processors are not efficient due to the nature of their mathematical algorithms.
Some processor design experiences show that the hardware must be designed and optimized based on nature of mathematical algorithms that they should execute. Moreover, the existing software platforms and libraries should be considered during the design of new hardware. We know that developing new software platforms for new hardware is time-consuming and expensive. The solution that is currently used is to use the existing software methods and libraries for new hardware for which they are not necessarily efficient for, a fruitless circle!
Is the Software a Nightmare for Xilinx Versal ACAP? Only time will tell.
Area Sales Manager at MACOM Technolgies Driving Business Growth and Engineering Solutions that Enable Customers to Deploy Differentiated Products and Services Focused on Leading Edge Technogies and Applications
5 年One more point. To quote you here: "We know that developing new software platforms for new hardware is time-consuming and expensive." You bet your marbles it is, but it's a necessity more so now than ever. My point earlier about silicon development costs comes courtesy of John Hruska at ExtremeTech, which does seem to align with industry opinion.?https://www.extremetech.com/computing/272096-3nm-process-node
Accelerating innovation: solving problems with high-performance compute
5 年Time has already told that building a compute fabric devoid of application requirements will always yield sub-optimal results. FPGAs only deliver 1% of the performance of what the silicon is capable of, and if your algorithm doesn't fit the DSP block architecture, you end up with noncompetitive price/perf points compared to GPUs or TPUs or even DSPs.? History is full of suckers that fell for the marketing ploy of being sold peak performance only to realize that real performance is nowhere near the marketing numbers.
SMTS Product Development Engineer at AMD
5 年In a month there will be an event called Xilinx Developper Forum: https://www.xilinx.com/products/design-tools/developer-forum.html A lot of announcements will be done and we will be able to say a lot more on the devices and the tools.
SMTS Product Development Engineer at AMD
5 年You'll have a lot of answers by the end of the year. Stay tuned!
Founder, Principal Consultant
5 年Parallel processing by architectures such as Versal will not be easy. However, there is no other way to sustain demand for compute power. Software folks like known to work libraries, but it will take cross-discipline efforts to optimise algorithms on such architectures. Just remember what IBM team did with 256 GPU cluster for ML training. Similar breakthrough performance is enabled by Versal.