SoCs with Analog or Mixed Signal IPs - Integration Challenges and Quality Checks

Analog or Mixed Signal IPs are an essential part of every SoC. These IP handles all the features on a chip that connects to the outside world to SOC whether it's inputs, output, Interfaces, Signal Conversion, Power Management, Power On reset, clock Signals, etc. In the real world, all the signals are analog signals and these signals are continuous variable signals representing some or other physical quantity. ?Digital Signal Processors (DSP) take real-world signals like voice, audio, video, temperature, pressure, or position that have been digitized and is the processing of analog signals in the digital domain. These IPs include Power on Reset (POR), Low-dropout regulators (LDO), Switch-mode power supplies (SMPS), Glitch detectors, Analog to Digital converters (ADCs), Digital to Analog converters (DACs), Oscillators, PLL/DLLs, Crystal oscillators, voltage monitor, IO pads, PHYs, SERDES, Low-Noise amplifiers (LNAs) and other analog IP’s. In the SOC even digital interfaces such as DDR pads or SerDes involve primarily analog IP, as digital signals are just a two-state approximation of an analog system.

Analog or Mixed Signal IPs bring challenges when design integration in System on Chip (SoC) designs. The reason is analog designs are sensitive to layout, floorplan, matching, signal swing, voltage level, drive impedance, Signal timing, and Power Management. The source of Input signals IO AC characteristic impacts design integration. Analog IP is provided as hard IP in the form of GDSII layout blocks which are fixed in size, tied to a particular foundry, or process, and are often difficult to integrate with SOC's digital designs. The main challenge is that Analog or Mixed Signal IPs need to be redesigned for every process, and often the correct configuration is not available off-the-shelf, customization is required to fit the design to the application. The challenges are because of reuse issues that come from Technology node change/migration, clock frequency, specification requirement, target foundry, usage application, and EDA tools. The big difference in analog IP integration is basically where is the source of IPs. For an analog IP design need to have specification for a circuit that needs to meet that is sort of a transmitter circuit or a receiver circuit that need to design?to meet some specification called IO AC characteristics(ACIO) that the actual source for what ends up on silicon there is starting from the schematic, it's not necessarily starting from the RTL.

The Global demand for the Analog?or Mixed Signal IPs Market as of 2022 is a valuation of US$ 72,351.6 Million and forecasted that by the end of 2030 sales revenue of US $200 Billion. The huge growth over the decade is predicted to progress by CAGR 9.76%

The Key drivers of Analog or Mixed Signal IPs are consumer electronics, the Automotive industry, Wireless communications, IOTG applications, and all general-purpose IPs. Consumer electronics such as Bluetooth players, tablets, smartphones, TVs, fitness trackers, smart watches, smart smoke detectors, thermostats, IP/Wi-Fi cameras, smart switches, smart locks,?sensors, and battery-powered consumer products worldwide. Due to the increased use of electronics in fuel efficiency, signals, emission reduction, navigation, entertainment systems, and advanced driver assistance systems (ADAS), semiconductor devices in Automotive Systems are boosting the demand for analog IPs. With the growing use of the Internet of things (IoT) usage like End users can sense, understand, and transfer intelligent data due to analog IPs. Because of the numerous advantages of using these IPs across a wide range of real-time connected devices and applications, the internet of things is predicted to promote the industry's growth. Further, general-purpose analog IPs have low power consumption and efficient signal processing capabilities, making them ideal for setting up an automated device ecosystem. The expansion of the telecommunications sector especially because of 5G and other technological developments in wireless technology and peripheral devices. The growing demand for environmental awareness for Power management analog IPs systems to handle wired and non-wired connections. By Application Analog IPs are required for Interface, Power Management, Signal Conversion, Amplifier/Comparators

The Global General Purpose Analog IPs Market is a moderately fragmented market with major players like Intel, Synopsys, NXP Semiconductors, STMicroelectronics, Infineon Technologies, Analog Devices, Inc, Texas Instruments Incorporated, Microchip Technology Inc, etc.

Any changes in Analog IP specification or late-finding bugs can cause tape-out delays, or SOC may not work properly due to rushed IP delivery. In addition, as customization work is often required, this can substantially increase the cost of the analog IP either upfront due to the engineering effort involved, or later due to the die area implications to the chip.

The same analog IP may not work in lower technology nodes because of Technology node change/migration. ?due to Voltage scaling impacting the signal-to-noise ratio and signal propagation time, Interconnect pitch scaling. This results in changes in the parasitic of interconnect and resulting signal integrity (SI) effects, ?The change in system clock frequency may lead to different noise coupling issues on the analog IP. In some cases specification change even at the same technology node necessitates design changes to meet performance requirements. Based on the target Foundry like Intel, TSMC, and Samsung can also require Analog IPs customization. The analog behavior for the same analog IP at a common technology node is due to the difference in process tech logy of the foundries. Changes in usage scenario with integration in different SoC: PLL integrated in wireless application with one digital clock frequency of SOC may not behave the same when compared with wireline application at a different frequency due to different noise environments, footprint constraints, or different modes of PLL operation.?The changes in EDA tools also impact Analog IP integration because of different device models leading to different simulation results.

The quality review is critical in Analog IPs performance on SOC design. The key checks are feature thoroughly verified in?RTL, MSV done with required simulations and fuse values, specs met on metrics like performance, power, area etc, IP better silicon proven if not IP risks and mitigation plans should published, constraints review with IP vendors, The final schematics & layout simulated across all corners (PVT) and required dynamic temp range(DTR), power states and with power-up and power-down sequence, extraction quality, no repeaters placed on analog nets, system level design review done with platform SI team for package interfacing Ips, electrical interoperability, SOC level parasitics bounded by providing routing constrains to SOC, For Pkg interfacing IP-?Is?worst case VIH/VIL verified, simulation with toggling static signals like en, pwrgood, dangling nodes/pins reviewed POR version of std cells collaterals, LEC/FEV done with UPF and is clean, behavior models (BMODs) for analog blocks reviewed and verification done for?equivalence between BMOD and Ckt. HVM features are fully validated with spice. Electrical performance validation, learnings from the latest Silicon (Previous product or Testchips,?aging run on analog blocks, clock uncertainty (jitter, dcd, etc),?PV Quality checked

Disclaimer: The opinions expressed within the content are solely the author's and do not reflect the opinions and beliefs of the company.

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