SOC Design Verification: Interview Questions
Vineet Singh
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UVM Questions
What is p_sequencer ?
What is a UVM RAL model ? Why is it required ?
What is an analysis port ?
What is the difference between new() and create() ?
Is UVM independent of SystemVerilog ?
Why do we need to register a class with a factory ?
What are Active and Passive modes in an agent ?
What is a TLM Fifo ?
What are the advantages of `uvm_component_utils and `uvm_object_utils ?
How does a sequence start ?
What are the different phases in UVM ?
What is a virtual sequence and a virtual sequencer ?
What is the difference between `uvm_do and `uvm_send ?
What is the difference between uvm_transaction and uvm_sequence_item ?
What are the benefits of using UVM ?
Can we have a user defined phase in UVM ?
What is the difference between RAL backdoor and frontdoor accesses ?
What is a phase objection ?
What is the difference between set_config_* and uvm_config_db ?
What are the different factory override types ?
How can we access a DUT signal in a component or sequence ?
What is RALGEN and how do you use it ?
What are desired and mirrored values in RAL ?
What are reg2bus and bus2reg functions for ?
How would you debug a config db name or path mismatch problem ?
What are the different TB components in UVM ?
Which phase takes more time and why ?
How do you connect a monitor with a scoreboard ?
How do you connect driver and sequencer ?
What is uvm_config_db and uvm_resource_db ?
What does a sequence normally contain ?
Write pseudo code for implementing an AHB-Lite driver.
System Verilog Questions
What is the difference between a deep copy and a shallow copy ?
What is the difference between initial and final block in SystemVerilog?
What is the purpose of this pointer in SystemVerilog ?
What is a virtual interface ?
What is the difference between $random and $urandom ?
What is the best way to avoid race conditions between DUT and testbench in a verification environment ?
Where is extern keyword used ?
What is a clocking block and why is it used ?
How can we reference variables and methods defined in the parent class from a child class ?
Explain the difference between pass by value and pass by reference.
What is the difference between rand and randc ?
Use $urandom_range to generate 8, 16, or 32. Does this give equal probability ?
Randomly generate 8, 16, 32, 64 with equal probability using SystemVerilog constructs.
What is the difference between data types logic and reg ?
What is the difference between mailbox and queue ?
Assume a class called "ABC" has been used throughout in a project. In a derivative project, you had to extend "ABC" to form "DEF" and add some more variables and functions within it. What will happen if you try to use an object of "ABC" that was created in the legacy testbench to access these new variables or functions ?
What are parameterized classes ?
Verilog Questions
What is the difference between a blocking and non-blocking assignment ?
Do all reg variables get synthesized into flops ?
What is $root used for ?
How can you ensure the synthesizable Verilog will build a sequential logic ?
Verification Questions
Why do we need to write random testcases ?
What is functional coverage and how is it useful ?
When can you say that verification is done ?
If functional coverage and code coverage is 100% after exclusions, can we stop doing verification ?
Assume your design can report 10 different types of errors, each flagged by a bit in an error register. The design also has a 10-bit output signal called error where each bit can be masked by an mask register. Once an error bit is set in the error register, it will be cleared on the next read. Write a small test plan.
System On Chip (SOC) Questions
What are linker scripts ?
How can you say that AMBA AHB protocol is pipelined ?
How many channels does an AXI master have ?
When is an AXI transfer considered to be valid ? Which signals would you look for ?
Misc Question
What are the different stages in a chip/ASIC/SoC design ?
C/C++ Question
Write the C code to exchange values of the MSB and LSB bits in a C integer variable.
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by Raju Prasad