Small-pitch LED display brings challenges to the chip side
Compared with other display technologies, LED display has the advantages of self-illumination, excellent color reproduction, high refresh rate, power saving, and easy maintenance. High brightness and ultra-large size through splicing are the decisive factors for the rapid growth of LED displays in the past two decades. In the field of ultra-large screen outdoor display, no other technology can compete with LED display technology.
Small pitch LED display
However, in the past, LED displays also had their shortcomings, such as the large spacing between the encapsulated lamp beads, resulting in low resolution, which is not suitable for indoor and close viewing. In order to improve the resolution, it is necessary to reduce the spacing between the lamp beads, but the size of the lamp beads is reduced, although it can improve the resolution of the whole screen, the cost will rise rapidly, and the excessive cost affects the large-scale commercial application of small-pitch LED displays.
In recent years, with the help of chip manufacturing and packaging manufacturers, IC circuit manufacturers and screen manufacturers, the cost of single-package devices is getting lower and lower, LED packaging devices are getting smaller and smaller, the pixel pitch of the display screen is getting smaller and smaller, and the resolution is getting higher and higher, making the advantages of small-pitch LED displays in indoor large-screen displays more and more obvious.
First, the demand for LED chips put forward by small-pitch LED displays
As the core of LED display, LED chips play a vital role in the development of small-pitch LEDs. The current achievements and future development of small-pitch LED displays rely on the unremitting efforts of the chip side.
On the one hand, the point spacing of indoor display screens has gradually decreased from the early P4 to P1.5, P1.0, and P0.8 under development. Correspondingly, the size of the lamp bead has been reduced from 3535 and 2121 to 1010, and some manufacturers have developed 0808 and 0606 sizes, and even some manufacturers are developing 0404 sizes.
As we all know, the size reduction of the package lamp beads inevitably requires the reduction of the chip size. At present, the surface area of blue-green chips for small-pitch display screens in the market is about 30mil2, and some chip factories have mass-produced 25mil2 or even 20mil2 chips.
On the other hand, the surface area of the chip becomes smaller, the brightness of the single core decreases, and a series of problems affecting the display quality have become prominent.
The first is the requirement for grayscale. Unlike outdoor screens, the difficulty of indoor screen demand is not brightness but grayscale. At present, the brightness demand of indoor large-pitch screens is about 1500 cd/m2 -2000 cd/m2, and the brightness of small-pitch LED displays is generally about 600 cd/m2 -800 cd/m2, and the optimal brightness of the display screen suitable for long-term attention is about 100 cd/m2 -300cd/m2.
At present, one of the problems of small-pitch LED screens is "low brightness and low gray". That is, there is not enough grayscale at low brightness. To achieve "low brightness and high gray", the current scheme used at the package end is a black bracket. Since the black bracket has a weak reflection on the chip, the chip is required to have sufficient brightness.
The second is the issue of display uniformity. Compared with the regular screen, the smaller pitch will cause problems such as afterglow, dark first sweep, low brightness and red, and low gray unevenness. At present, efforts have been made to effectively alleviate these problems in response to problems such as afterglow, first sweep dimming and low gray red, and the problem of brightness uniformity at low grayscale has also been alleviated by point-by-point correction technology. However, as one of the root causes of the problem, the chip side needs more effort. Specifically, the brightness uniformity at small currents is good, and the consistency of parasitic capacitance is good.
The third is the issue of reliability. The current industry standard is that the allowable value of LED dead light rate is one in ten thousand, which is obviously not suitable for small-pitch LED displays. Due to the large pixel density of the small-pitch screen and the close viewing distance, if there is 1 dead light in 10,000, the effect is unacceptable. In the future, the dead light rate needs to be controlled at one part per 100,000 or even one part per million to meet the needs of long-term use.
In general, the development of small-pitch LEDs puts forward the requirements for chip segments: size reduction, relative brightness improvement, good brightness consistency at small current, good parasitic capacitance consistency, and high reliability.
Second, the chip-side solution??
1. Size reduction, chip size reduction
On the surface, it is a problem of layout design, which seems to be solved by designing smaller layouts according to needs. But can the reduction in chip size continue indefinitely? The answer is no. There are several reasons that limit the degree of chip size reduction:
(1) Restrictions on packaging processing. During the packaging process, two factors limit the reduction of chip size. One is the limitation of the suction nozzle. Solid crystals need to absorb the chip, and the size of the short side of the chip must be larger than the inner diameter of the nozzle. At present, the inner diameter of the cost-effective nozzle is about 80um. The second is the limitation of the bonding wire. The first is the wire bonding tray, that is, the chip electrode must be large enough, otherwise the reliability of the wire bonding wire cannot be guaranteed, and the industry reports that the minimum electrode diameter is 45um; Secondly, the spacing between the electrodes must be large enough, otherwise the two bond wires will inevitably interfere with each other.
(2) Restrictions on chip processing. In the process of chip processing, there are also two limitations. One is the limitation of layout layout. In addition to the above restrictions on the package end, electrode size, electrode spacing requirements, electrode distance from MESA, delineation width, boundary line spacing of different layers, etc. have their limits, chip current characteristics, SD process capabilities, lithography processing capabilities determine the scope of specific limits. Typically, the minimum distance from the P-electrode to the edge of the chip is limited to more than 14 μm.
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The second is the limitation of scratching processing capacity. The SD dicing + mechanical slobe process has limits, and the chip size is too small to prevent the splinter. As the wafer diameter increases from 2 inches to 4 inches, or in the future to 6 inches, the difficulty of dicing slobes increases, which means that the size of the chip that can be processed increases. Taking a 4-inch chip as an example, if the short side length of the chip is less than 90μm and the aspect ratio is greater than 1.5:1, the yield loss will increase significantly.
Based on the above reasons, the author boldly predicts that after the chip size is reduced to 17mil2, the chip design and process processing capacity is close to the limit, and there is basically no room for reduction, unless there is a big breakthrough in the chip technology solution.
2. Brightness boost
Brightness improvement is the eternal theme on the chip side. The chip factory improves the internal quantum effect through epitaxial program optimization, and the external quantum effect through chip structure adjustment.
However, on the one hand, the reduction of chip size will inevitably lead to a reduction in the area of the light-emitting area and a decrease in the brightness of the chip. On the other hand, the dot pitch of small-pitch displays is reduced, and the demand for single-chip brightness is reduced. There is a complementary relationship between the two, but there must be a bottom line. At present, in order to reduce costs, the chip side mainly does subtraction in the structure, which usually has to pay the price of reducing brightness, so how to weigh the trade-off is a problem that the industry should pay attention to.
3. Consistency at small currents
The so-called small current is relative to the current of conventional indoor and outdoor chip trials. The chip I-V curve shown in the figure below, conventional indoor and outdoor chips work in linear working areas, and the current is large. The small-pitch LED chip needs to work in a nonlinear operating area close to the 0 point, and the current is small.
In the nonlinear operating area, LED chips are affected by semiconductor switching thresholds, and the difference between chips is more pronounced. The discretization of brightness and wavelength of high-volume chips is easy to see that the discreteness of the nonlinear working area is much greater than that of the linear operating area. This is an inherent challenge on the chip side today.
The solution to this problem is first of all the optimization of the extension direction, mainly to reduce the lower limit of the linear working area; The second is the optimization of chip spectroscopy to distinguish chips with different characteristics.
4. Parasitic capacitance consistency
At present, there is no condition to directly measure the capacitance characteristics of the chip on the chip side. The relationship between capacitance characteristics and conventional measurement items is unclear and remains to be summarized. The direction of chip-side optimization is firstly epitaxy adjustment, and the other is refinement on electrical binning, but the cost is high and is not recommended.
5. Reliability
Chip-side reliability can be described in terms of parameters in the chip packaging and aging process. But in general, the factors influencing the reliability after the chip on the screen focus on ESD and IR.
ESD refers to antistatic ability. According to IC industry reports, more than 50% of chip failures are related to ESD. To improve chip reliability, ESD capabilities must be enhanced. However, under the condition of the same epitaxial wafer and the same chip structure, the smaller chip size will inevitably lead to the weakening of ESD ability. This is directly related to the current density and chip capacitance characteristics and cannot be resisted.
IR stands for reverse leakage, which is usually measured at a fixed reverse voltage to measure the reverse current value of the chip. IR reflects the number of defects inside the chip. The higher the IR value, the more internal defects of the chip.
To improve ESD capability and IR performance, more optimization must be made in terms of epitaxial structure and chip structure. When the chip is classified, through strict binning standards, chips with weak ESD capabilities and IR performance can be effectively eliminated, thereby improving the reliability of the chip after the screen.
Third, summary
In summary, with the development of small-pitch LED displays, the LED chip side faces a series of challenges, and gives improvement plans or directions one by one. It should be said that there is still a lot of room for the optimization of LED chips. How to improve, but also unemployed people to exert their wisdom, continuous efforts.