Sketch a circuit out of Verilog code
Anoushka Tripathi
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Anoushka Tripathi
Winner @DIR-V Symposium Hackathon|FPGA Trainee @SSPL DRDO, Ministry of Defence, Govt. of India|Founder @Bharatiya Silicon Innovators|RISC V Design & Verification|Final year|VLSI Engineer|Bhāratīya
Here we will interpret a circuit with help of visualization
OR
You can say we will sketch a circuit out of a verilog code
module foo (CE, X, CLK, RST, OUT);
input CE, CLK, X, RST;
output OUT;
reg [3:0] Q1;
reg [3:0] Q2;
assign OUT = ^Q1;
always @ (posedge CLK)
if (RST) begin
Q1 <= 4'h5;
Q2 <= 0;
end
else
if (CE) begin
if (X) Q2 <= Q1<<1;
else Q2 <= Q1;
Q1 <= Q2;
end
endmodule
The declaration
At last xor the 4 bits of Q1 and send to output
Thank you so much....
Project Intern at URSC, ISRO || Former President of JeevYantra, Robotics Club IIST || B.Tech ECE (Avionics) final year student at Indian Institute of Space Science and Technology | Learner
1 年Your explanation of the Verilog circuit is clear and easy to follow. Great job!