SiP packaging technology

Beyond Moore-Introduction to SiP

According to the definition of the International Semiconductor Route Organization (ITRS): SiP is a single unit that combines multiple active electronic components with different functions, optional passive devices, and other devices such as MEMS or optical devices to achieve certain functions. Standard packages form a system or subsystem.

In terms of architecture, SiP integrates multiple functional chips, including processors, memory and other functional chips in a package, so as to achieve a basically complete function. Corresponds to SOC (System on Chip). The difference is that system-in-package is a packaging method in which different chips are used side by side or stacked, while SOC is a highly integrated chip product.

1.1. More Moore VS More than Moore——Comparison of SoC and SiP

SiP is an important realization path beyond Moore's Law. Where is the well-known Moore's Law developed to this stage? There are two paths in the industry: One is to continue to develop in accordance with Moore's Law. Products that follow this path include CPU, memory, and logic devices, and these products account for 50% of the entire market. The other is the More than Moore route beyond Moore's Law. Chip development has shifted from blindly pursuing power consumption reduction and performance improvement to more pragmatically satisfying market demands. Products in this area include analog/RF devices, passive devices, power management devices, etc., accounting for approximately the remaining 50% of the market.

SoC and SIP are very similar. Both integrate a system containing logic components, memory components, and even passive components into one unit. SoC is from a design point of view, which is to highly integrate the components required by the system onto a chip. SiP is based on the packaging standpoint. Different chips are packaged side-by-side or stacked, and multiple active electronic components with different functions and optional passive devices, as well as other devices such as MEMS or optical devices, are preferentially assembled together. , A single standard package that realizes certain functions.

From the perspective of packaging development, SoC has been established as the key and development direction of future electronic product design due to the needs of electronic products in terms of volume, processing speed, or electrical characteristics. However, with the increasing cost of SoC production in recent years, frequent technical obstacles have caused the development of SoC to face a bottleneck, and the development of SiP has been paid more and more attention by the industry.

1.2. SiP-an inevitable path beyond Moore's Law

Moore's Law ensures the continuous improvement of chip performance. As we all know, Moore's Law is the "bible" for the development of the semiconductor industry. On silicon-based semiconductors, the feature size of transistors is reduced by half and performance is doubled every 18 months. While the performance is improved, the cost is reduced, which gives semiconductor manufacturers enough motivation to achieve the reduction of semiconductor feature size. Among them, processor chips and memory chips are the two types of chips that most obey Moore's Law. Taking Intel as an example, each generation of products perfectly follows Moore's Law. At the chip level, Moore's Law promotes the continuous advancement of performance.

SIP is the winner in solving the shackles of the system. Packaging multiple semiconductor chips and passive components in the same chip to form a system-level chip, instead of using a PCB as a carrier between chip connections, it can solve the system performance caused by the inherent deficiencies of the PCB. Encountered a bottleneck problem. Take the processor and memory chip as an example, because the internal trace density of the system-in-package can be much higher than the PCB trace density, thereby solving the system bottleneck caused by the PCB line broadband. For example, because the memory chip and the processor chip can be connected by perforation, they are no longer limited by the PCB line width, so that the data bandwidth can be improved in the interface bandwidth.

SiP process analysis

The SIP packaging process can be divided into wire bond packaging and flip-chip soldering according to the connection mode of the chip and the substrate.

2.1. Wire bond packaging process

The main flow of the wire bonding packaging process is as follows:

Wafer→wafer thinning→wafer cutting→chip bonding→wire bonding→plasma cleaning→liquid encapsulant potting→assembly solder ball→reflow soldering→surface marking→separation→final inspection→test→packaging.

Wafer thinning

Wafer thinning refers to the use of mechanical or chemical mechanical (CMP) grinding from the back of the wafer to reduce the thickness of the wafer to a level suitable for packaging. As the size of the wafer is getting larger and larger, in order to increase the mechanical strength of the wafer and prevent deformation and cracking during processing, its thickness has been increasing. However, as the system develops in the direction of lighter, thinner and shorter, the thickness of the module becomes thinner after the chip is packaged. Therefore, the thickness of the wafer must be reduced to an acceptable level before packaging to meet the requirements of chip assembly.

Wafer cutting

After the wafer is thinned, it can be diced. Older dicing machines are manually operated, and now the general dicing machines are fully automated. Whether it is partly scribing or completely dividing the silicon wafer, a saw blade is currently used, because the edges it scribes are neat, and there are few chips and cracks.

Die bonding

The chip that has been cut should be mounted on the middle pad of the frame. The size of the pad must match the size of the chip. If the size of the pad is too large, the lead span will be too large. During the transfer molding process, the lead will bend and chip displacement due to the stress generated by the flow. The mounting method can be soldered to the substrate with soft solder (referring to Pb-Sn alloy, especially alloy containing Sn), Au-Si eutectic alloy, etc. The most commonly used method in plastic packaging is to use polymer bonding The binding agent is glued to the metal frame.

Wire bonding

The lead wire used in plastic packaging is mainly gold wire, and its diameter is generally 0.025mm~0.032mm. The length of the lead is often between 1.5mm~3mm, and the height of the arc can be 0.75mm higher than the plane where the chip is located.

The bonding technology includes hot pressure welding, thermosonic welding and so on. The advantages of these technologies are that it is easy to form a spherical shape (that is, solder ball technology) and prevent the oxidation of the gold wire. In order to reduce costs, other metal wires, such as aluminum, copper, silver, palladium, etc., are also being used to replace gold wire bonding. The condition of hot pressure welding is that the two metal surfaces are in close contact, and the time, temperature, and pressure are controlled to make the two metals connect. Rough surface (unevenness), oxide layer formation, chemical contamination, moisture absorption, etc. will affect the bonding effect and reduce the bonding strength. The temperature of hot-press welding is between 300°C and 400°C, and the time is generally 40ms (usually, with programs such as finding the bonding position, the bonding speed is two lines per second). The advantage of ultrasonic welding is that it can avoid high temperature, because it uses 20kHz~60kHz ultrasonic vibration to provide the energy required for welding, so the welding temperature can be lowered. The use of heat and ultrasonic energy for bonding at the same time is the so-called thermosonic welding. Compared with thermal compression welding, the biggest advantage of thermosonic welding is to reduce the bonding temperature from 350°C to about 250°C (some people think that the conditions of 100°C~150°C can be used), which can greatly reduce the bonding temperature on the aluminum pad. The possibility of forming Au-Al intermetallic compounds extends the life of the device and reduces the drift of circuit parameters. Improvements in wire bonding are mainly due to the need for thinner and thinner packages. Some ultra-thin packages are only about 0.4mm thick. Therefore, the loop of the lead wire is reduced from the general 200 μm~300 μm to 100μm~125μm, so the lead wire tension is very large and tight. In addition, there are usually two ring-shaped power/ground wires around the lead pads on the substrate. The gold wire must be prevented from short-circuiting with it during bonding. The minimum gap must be >625 μm, and the bonding wires must have high linearity. And a good arc.

Plasma cleaning

One of the important functions of cleaning is to improve the adhesion of the film, such as depositing an Au film on a Si substrate, and treating the surface with Ar plasma to remove hydrocarbons and other contaminants, which significantly improves the adhesion of Au. The surface of the substrate after plasma treatment will leave a layer of gray substance containing fluoride, which can be removed with a solution. At the same time, cleaning also helps to improve surface adhesion and wettability.

Liquid sealant potting

Place the chip and wire bonding frame tape in the mold, and heat the preformed block of plastic molding compound in a preheating furnace (the preheating temperature is between 90℃ and 95℃), and then put it into the transfer In the transfer tank of the forming machine. Under the pressure of the transfer molding piston, the molding compound is squeezed into the runner and injected into the cavity through the gate (in the whole process, the mold temperature is maintained at about 170°C~175°C). The molding compound is rapidly solidified in the mold, and after a period of holding pressure, the module reaches a certain hardness, and then the module is ejected with the ejector rod, and the molding process is completed. For most molding compounds, after a few minutes of holding pressure in the mold, the hardness of the module is sufficient to allow ejection, but the curing (polymerization) of the polymer is not completely completed. Since the degree of polymerization (curing degree) of the material strongly affects the glass transition temperature and thermal stress of the material, it is very important to improve the reliability of the device to promote the curing of the material to achieve a stable state. Post-curing is to improve the molding compound The process steps necessary for the high degree of polymerization, the general post-curing conditions are 170℃~175℃, 2h~4h.

Liquid sealant potting

There are two methods of planting balls currently used in the industry: "solder paste" + "solder ball" and "solder paste" + "tin ball". The "solder paste" + "tin ball" ball planting method is recognized as the best standard ball planting method in the industry. The balls planted by this method have good solderability and good gloss, and there will be no solder ball offset during the melting process. , It is easier to control. The specific method is to first print the solder paste on the BGA pad, and then use a ball machine or screen printing to add a certain size of solder ball on it, then the role of the solder paste is to stick the tin When heating, the contact surface of the solder ball is made larger, so that the solder ball is heated faster and more comprehensively, so that the solder ball can be better welded to the pad after melting and reduce the possibility of false soldering.

Surface marking

Marking is to print unremovable, clearly written letters and logos on the top surface of the packaged module, including manufacturer information, country, device code, etc., mainly for identification and tracking. There are many coding methods, among which the most commonly used is the printing method, which includes ink printing and laser printing.

Separate

In order to improve production efficiency and save materials, most of the SIP assembly work is carried out in an array combination. After the molding and testing procedures are completed, it is divided and divided into individual devices. Dividing and dividing can use sawing or stamping processes. The sawing process is more flexible and does not require many special tools. The stamping process has higher production efficiency and lower cost, but requires the use of special tools.

2.2. Flip chip welding process

Compared with wire bonding process, flip-chip bonding process has the following advantages:

(1) Flip-chip bonding technology overcomes the problem of the center distance limit of wire bonding pads;

(2) Provide more convenience to electronic designers in the design of chip power/ground distribution;

(3) By shortening the interconnection length and reducing the RC delay, it can provide more perfect signals for high frequency and high power devices;

(4) Excellent thermal performance, a heat sink can be installed on the back of the chip;

(5) High reliability. Due to the effect of the filler under the chip, the fatigue life of the package is enhanced;

(6) Easy to repair.

The following is the process flow of flip-chip bonding (the same process as wire bonding will not be described separately): wafer → pad redistribution → wafer thinning, production of bumps → wafer cutting → flip-chip bonding, Underfill → encapsulate → assemble solder ball → reflow soldering → surface marking → separation → final inspection → test → packaging.

Land redistribution

In order to increase the lead spacing and meet the requirements of the flip-chip bonding process, it is necessary to redistribute the leads of the chip.

Make bumps

After the pad redistribution is completed, it is necessary to add bumps to the pads on the chip. The solder bump production technology can adopt electroplating, electroless plating, evaporation, ball placement and solder paste printing. At present, the electroplating method is still the most widespread, followed by the solder paste printing method.

Flip chip bonding, underfill

After the solder bumps are arranged on the entire chip bonding surface according to the grid shape, the chip is mounted on the package substrate in an inverted manner, and the bumps are electrically connected to the pads on the substrate, instead of WB and TAB. Connection method. After the flip-chip bonding is completed, the epoxy resin is used to fill the gap between the chip and the substrate, which can reduce the thermal stress and mechanical stress applied to the bumps, and the reliability is improved by one to two orders of magnitude compared to the reliability without filling.

SiP-born for applications

3.1. Main application areas

SiP has a wide range of applications, including: wireless communications, automotive electronics, medical electronics, computers, military electronics, etc.

The most widely used wireless communication field. SiP has the earliest application in the field of wireless communication and is also the most widely used field. In the field of wireless communication, requirements for functional transmission efficiency, noise, volume, weight, and cost are getting higher and higher, forcing wireless communication to develop in the direction of low cost, portable, multi-function and high performance. SiP is an ideal solution that combines the advantages of existing core resources and semiconductor production processes, reduces costs, shortens time to market, and overcomes difficulties in SOC such as process compatibility, signal mixing, noise interference, and electromagnetic interference. The radio frequency power amplifier in the mobile phone integrates the functions of frequency power amplifier, power control and transceiver switch, which is completely solved in SiP.

3.2.SiP-tailored for smartphones

The thinning of mobile phones has brought growth in SiP demand. Mobile phones are the largest market for SiP packaging. As smart phones become thinner and lighter, the demand for SiP will naturally increase. From 2011 to 2015, the thickness of mobile phones of various brands has been continuously reduced. Thinning naturally places higher and higher requirements on the thickness of assembled parts. Taking the iPhone 6s as an example, the PCB usage has been greatly reduced, and many chip components will be included in the SiP module, and the iPhone 8 may be Apple’s first full-machine SiP mobile phone. This means that on the one hand, the iPhone 8 can be made thinner and lighter, and on the other hand, there will be more room for other functional modules, such as a more powerful camera, speakers, and battery.

Touch chip. In Iphone6, there are two touch chips, which are provided by Broadcom and TI respectively. In 6S, the two are sealed in the same package to realize the SiP package. In the future, TDDI will be further packaged together. The new generation of 3D Touch technology is demonstrated in iPhone6s. The touch sensing detection can penetrate the insulating material shell, and by detecting the voltage change brought by the human finger, the touch action of the human finger can be judged, so as to realize different functions. The touch chip is to collect the voltage values of the contact points, process these electrode voltage signals and convert them into coordinate signals, and control the mobile phone to respond to the corresponding functions according to the coordinate signals, thereby realizing its control function. The emergence of 3D Touch puts forward higher requirements for the processing capacity and performance of the touch module. Its complex structure requires that the touch chip be assembled with SiP, and the tactile feedback function enhances its operational friendliness.

The fingerprint recognition also uses the SiP package. Packaging the sensor and the control chip together, starting with iPhone 5, a similar technology has been adopted. HOREXS specializes in the production of fingerprint recognition ultra-thin circuit boards for more than ten years, with stable quality, and has achieved a 100% pass rate in the SIP packaging process.

The rapidly growing SiP market

4.1. Market scale & penetration rate rapidly increase

2013-2016 SiP market CAGR=15%. In 2014, the global SiP output value was approximately 4.84 billion U.S. dollars, an increase of about 12.4% compared to 2013; in 2015, with the continued growth of smart phones and the advent of wearable products such as Apple Watch, the global SiP output value is estimated to reach 5.533 billion U.S. dollars, compared with 2014 Annual growth rate of 14.3%.

In 2016, although smart phones may gradually enter the mature stage and it is difficult to achieve substantial growth, SiP can still show a growth trend under the trend of increasing popularity. Therefore, it is estimated that the global SiP output value in 2016 will still be It has grown by 17.4% from 2015 to US$6.494 billion.

We estimate the market size of SiP in the smartphone market in the next three years. Assume that the unit price of SiP is reduced by 10% each year, and smartphone shipments increase by 3% annually. It can be seen that the new market scale of SiP in smart phones is CAGR=192%, which is very impressive.

One article understands SiP packaging technology, and beginners can understand the explanation!

4.2. From manufacturing to packaging and testing-the gradually integrated SiP industry chain

From the perspective of changes in the industrial chain and industrial structure, the electronics industry chain will no longer be just a traditional vertical chain in the future: terminal equipment manufacturers-IC design companies-packaging and testing manufacturers, Foundry factories, IP design companies, product development The design will simultaneously mobilize packaging manufacturers, substrate manufacturers, material plants, IC design companies, system manufacturers, Foundry plants, device manufacturers (such as TDK, Murata), and storage manufacturers (such as Samsung) to collaborate with each other to jointly achieve industrial upgrading. In the future, the system will drive the further development of the packaging industry, while high-end packaging will also promote the prosperity of system terminals. In the future, there will be more and more direct connections between system manufacturers and packaging factories, and IC design companies may develop in two directions: IP design or direct wafer sales.

One article understands SiP packaging technology, and beginners can understand the explanation!

Since it is almost difficult for packaging and testing plants to enter the field of foundry upstream, wafer foundries can step into downstream packaging and testing based on the advantages of process technology, especially in the field of high-end SiP; therefore, foundries Entering the SiP packaging business will shift from a purely upstream and downstream cooperation relationship with packaging and testing plants to a subtle competition and cooperation relationship.

On the one hand, the packaging and testing plant can develop towards differentiation to separate the market. On the other hand, it can also choose to conduct technical cooperation with the foundry, or use technology authorization and other methods to match the huge production capacity of the packaging and testing plant to take orders. To expand the market together. In addition, for the high-end heterogeneous packaging developed by the foundry, some of the process steps still require the assistance of professional packaging and testing plants with existing technology, so the two sides still have a basis for cooperation.

SiP represents the development direction of the industry. Chip development has shifted from blindly pursuing power consumption reduction and performance improvement (Moore's Law) to more pragmatically satisfying market needs (beyond Moore's Law). SiP is an important path to achieve. From the perspective of terminal electronic products, SiP does not blindly pay attention to the performance/power consumption of the chip itself, but realizes the entire terminal electronic product to be light, thin, short, multifunctional, and low power consumption. After the rise of lightweight products such as mobile devices and wearable devices, The demand for SiP is becoming increasingly apparent.

The penetration rate of SiP in smartphones is rapidly increasing. The 2013-2015 CAGR of the SiP market reached 16%, which was higher than the 7% CAGR of the smartphone market. As the trend of thinner and lighter smartphones is determined, the penetration rate of SiP will increase rapidly, and is expected to increase from 10% now to 40% in 2018. We emphasize that we must pay attention to any new changes in smart phones, before reaching a penetration rate of 40%, it is a period of rapid growth that deserves attention.

From the perspective of industry configuration, SiP has not yet been fully priced in, and there is room for growth. HOREXS is currently one of the first thin-sheet manufacturers in China. Since SIP has not yet been fully developed, HOREXS is currently investing in research and development every year before it is technically brave. At the same time, Apple has determined to use multiple SiPs in new models, but domestic manufacturers have not yet started to keep up. We estimate that the potential SiP incremental space in 2018 is 9.6 billion U.S. dollars. From the perspective of industry configuration, the current growth of SiP has not been fully recognized by the market, and there is enough room for growth. We believe that domestic HORES will benefit deeply from the development of the SiP industry and recommend cooperation.

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