Practical challenges faced by the designers in the stage of signal routing of system designs are the following:
- Routing process is a compute intensive process requiring machines of large com- putational power due to routing of many billions of signals. Many times, the pro- cess stops due to the lack of processing resource when algorithm is searching for the optimal net from large number of routing options in a congested part of the design and trying to optimize the design for multiple corner timing and signal integrity. The processing power needed to route the signal differs in such a sce- nario of the chip design compared to routing a simple non-congested block of the chip. This calls for a flexibility adding and removing the processing elements or CPUs dynamically as needed by the process. This is addressed in recent times by an option called elastic CPU or scalable CPUs by which one can add or remove CPUs dynamically during run times. User sets the option of available processor cores for the routing run and algorithm automatically uses them based on need.
- Additionally, signal routing faces complexity in optimizing multiple goals such as timing, signal integrity, and adherence to design constraints. Mitigating this challenge involves setting appropriate effort levels and constraints, tailored to the design's intricacy. Critical blocks are often routed separately, and designers specify key goals, whether focused on signal integrity, timing, or area. Given the compute-intensive nature of signal routing, designers leverage scalable CPU platforms and cloud computing to enhance efficiency while ensuring compliance with design constraints and DRC rules. These strategies contribute to a more streamlined and adaptable signal routing process in SoC design.
