Samsung reveals backside power technology research for the first time: chip area reduced by 14.8 per cent

TSMC, Samsung, Intel and other wafer fabrication manufacturers are actively laying out the back-side power supply network technology (BSPDN), and will be introduced into the development of cutting-edge logic process blueprint. Recently, Samsung Electronics announced BSPDN (backside power supply network) research results. This is the first time Samsung Electronics disclosed BSPDN-related specific research results.?

Electronic Engineering Album News TSMC, Samsung, Intel and other wafer fabrication manufacturers are actively laying out the backside power supply network technology (BSPDN), and will be introduced into the development of cutting-edge logic process blueprint. Recently, Samsung Electronics announced the BSPDN (backside power supply network) research results. This is the first time that Samsung Electronics has disclosed specific research results related to BSPDN.?

BSPDN is a concept first introduced at IMEC 2019. It is a design structure that improves power and signal lines as well as battery utilisation bottlenecks by arranging power wiring on the backside of the wafer.

Current semiconductors are made using the FSPDN structure. They are arranged in the order of power lines-signal lines-transistors, but problems such as bottlenecks occur because power and signal lines use the same resources. There is also the disadvantage of consuming a large amount of cost to expand the wiring layer depending on the expansion of the transistors.

Unlike existing semiconductor structures, BSPDNs are arranged in the order of signal lines - transistors - power lines. In a paper presented at the Japan VLSI Symposium at the end of June this year, Samsung Electronics claimed that it had succeeded in reducing the processor area by 14.8 per cent by applying the BSPDN compared with the FSPDN (Front Side Power Supply Network). Specifically, in two ARM circuits, the area was reduced by 10.6% and 19% respectively. This also means a reduction in cost and power consumption. It also means that the number of transistors inside the chip can be increased by 10 to 19 per cent if the chip area remains unchanged, and performance is expected to increase by 10 to 19 per cent. In addition to this, the backside power supply technology also reduces the length of the wiring by 9.2%.

Samsung Electronics also explained the technical difficulties of BSPDN. When BSPDN is applied, tensile stress acts and can separate the silicon through-hole electrode (TSV) from the metal layer. Samsung Electronics said that this problem can be solved by reducing the height or widening the TSV.

In addition to Samsung Electronics, Intel also announced its name "PowerVia" back power supply technology, will be introduced into the Intel 20A process. Intel also held a Powervia technology briefing last June. The goal of these companies is to start applying BSPDN from the 2nm process.

Based on a test chip from Intel's Blue Sky Creek, which uses the P-Core performance core from Intel's upcoming PC processor, Meteor Lake, PowerVia proves to be a solution to the problems caused by the old "pizza-style" manufacturing method, where the power and interconnect cables were separated and made larger to improve both power and signal transmission. The power and interconnect cables can be separated and made larger to improve both power and signal transmission. Tests have shown that standard cell utilisation exceeds 90% in most areas of the chip, while cell density has increased dramatically, with the prospect of cost reductions. Tests also showed that PowerVia reduced platform voltage by 30 per cent and achieved a 6 per cent frequency benefit, and the PowerVia test chip also demonstrated good thermal characteristics, in line with the higher power densities expected to be achieved by logic microsegmentation.

The industry recognises the importance of chemical mechanical polishing (CMP) technology to ensure backside wafer processing and TSV technology for signal and power line connections for BSPDN applications. TSMC will mass-produce its 2nm (N2) process in 2025 and plans to launch its N2P process in 2026, a process that will also feature backside power technology.

Samsung has yet to reveal when it plans to implement its BSPDN and which node it will use. The company is currently refining its second-generation SF3 manufacturing technology based on ring-gate transistors at the 3nm level, with volume production planned for 2024. The company also has SF3P and 2nm SF2 coming in 2025. While Samsung is unlikely to use backside power rails in SF3 next year, the company may consider implementing its BS PDN in SF3P or SF2 in 2025.