RTL Linting :
MANOJ KUMAR ROKKAM
Design Verification Trainee | Digital | Verilog | System Verilog | UVM |SVA| STA | CDC | DFT | 3X Global Certifications in Design & Verification
What is RTL Linting?
RTL Linting is a process that uses defined Rulesets & Policies applied to an RTL design before simulation to verify whether the RTL code has followed specified coding rules, Which causes synthesis issues and functional bugs at an early stage.
Why RTL Linting?
To prevent Functional bugs before synthesis and provide a bug-free design, Linting provides a report that allows us to check that the RTL design follows the specification-defined rules and policies by providing us with a Report. The Report contains information about how our RTL Design will work according to the rules and policies. Lint assigns severity to bugs, followed by Fatal, Error, Warning, and Info.
How does RTL Linting Happen?
->The lint tool uses policies & rule sets and does a static code analysis of the RTL Design, ->Once these rules are executed if the design source code doesn't obey to the ruleset or policies violation will be reported in the form of a Fatal, Error, Warning and Info. ->Fatal causes Lint run to abort ->Error apply to construct which causes incorrect operations ->Warning points out the area of the design that needs to be reviewed before design can be simulated ->Info is for information message only.
Types of Lint Checks:
Semantic checks - Incomplete case statements, default statement missing conditions, width mismatch ... Synthesizability checks - non-synthesizable subsets, use of both clock edges ... Structural Analysis - combinational loops, latches, tri-states, unused gates, floating nets.. Format lint - unreachable FSM states, missing FSM state transitions...... These and all need to be checked. Some Designs intentionally need bugs for them we do have a waiving concept in the Lint to waive that particular error to avoid or neglect its validation while linting.
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Where do we do this Linting?
In the present market, there are several paid and open-source lint tools available. Paid Tools: Synopsys VC Spyglass Free Tools: Verilator
Here I am posting a sample lint report of my present working project, for reference.
Thanks for reading and gaining lint knowledge Congratulations on your future endeavors.
R&D Engineer at Koshin Ltd
1 个月Very informative