RTL Engineer/HW-Bangalore

Interested candidate kindly send me your resume to [email protected] / 7259699404

Position: RTL Engineer/HW

Exp: 8-13 years.

The successful candidate will be involved in hands-on implementation of complex networking ASIC and will be responsible for IP/ sub-system level micro-architecture development and RTL coding. He/She will work on every aspect of ASIC design, working closely with the SW, collaborating design and verification teams. Specifically, the candidate will be responsible for designing networking products for the protocols like iWarp/RDMA, TCP/IP, iSCSI, L2/L3 Switching, routing etc. The ideal candidate would have owned complex design modules and taken it from concept to silicon. Must have good understanding of digital design fundamentals and a strong back ground of ASIC design and having experience in any of the industry standard tools. Should be conversant with synthesis and timing closure flows and concepts.

A minimum of about 7 years’ experience in RTL design preferably as part of the complex ASIC/SoC design

·       Design experience with any of high speed memory interfaces such as DDR is a big plus

·       Design experience with integrating embedded processors in an SoC design

·       Proficient in RTL design using Verilog and in verification languages

·       Hands on experience with Synthesis and timing closure flows.

·       Preferably has some standard external bus protocols like AMBA – ACP/AXI/AHB/APB.

·       Must be willing to learn and become proficient in networking protocols.

·       Desirable to have candidate with a back ground in architecture definition.

·       Desirable to have experience with low power design.

·       Exposure to mixed signal design and backend flow is desirable but not must.

Regards

Vikas

ConnectPro Management Consultants Pvt Ltd.