RISC-V Summit 2022
The RISC-V Summit took place in December. It was in person and virtual. Clearly, in the world of processors, RISC-V is the most important development of the decade. It has already taken over academia completely. It has a huge footprint in the embedded space. And this year, for the first time, many high-end processors that have been in stealth development for several years were on display.
I first came across RISC-V at EDPS in 2016, and then again later that same year when Krste Asanovic presented it at DAC. I recently wrote a sort of tutorial on RISC-V as a prelude to the summit. So you can read my posts:
If you don't know much about RISC-V, I recommend you read the tutorial before reading the rest of this post.
Calista Redmond
The summit opened with a keynote by Calista Redmond, the CEO of RISC-V International.
I actually met her in her previous gig, doing a similar job for the OpenPower Consortium, getting more people to use the open version of the PowerPC architecture.?But the PowerPC architecture was originally created by IBM, Apple, and Motorola, and today only IBM still uses it (for high-end servers), which is going in the wrong direction.
But RISC-V is booming.
RISC-V membership grew 26% this year and now has over 3,180 members (I say "over" since Calista said two more people had joined just that morning, so her slide was already out of date).
The three big points Calista made (and which Krste would return to in his "state of the union" keynote the following day) were: