RISC V - Part 3

Instruction set, Opcodes and Assembly Instructions

Instruction Set: It comprises the various groups of instructions that the processor can understand. Typical instruction set comprises memory read, memory write, logical operations, conditional jumps, unconditional jumps, compare , arithmetic operations, boolean operations and special instructions to check and manipulate the special registers.

RISC-V, RV32I Instructions can be classified as

• Immediate (LW, LH, LHU, LB, LBU, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, JALR)
• Register/Register (ADD/SLT/SLTU,OR,XOR,SLL,SRL,SUB,SRA)
• Store (SW,SH,SB)
• Upper Immediate (LUI, AUIPC)
• Branch (variation of Store) (BEQ,BNE,BLT,BGE,BLTU,BGEU)
• Jump (variation of Upper Immediate) (JAL)

Opcode: Opcode is the Hex equivalent of the instruction encoded based on the architecture of the CPU and the number of operands.

A simple ADD instruction of R type has bits 0 to 6 as opcode. = 0110011

Assembly Language instruction: The opcode along with the operands form the instruction. To use the add instruction we need it to be in the R format

| funct7 | rs2 | rs1 | funct3 | rd | opcode |

ADD x1,x2,x3

here ,

x1 is the destination

x2 and x3 are the source registers

The operations can be represented as :

x1 <- x2 + x3

Representation:

1. opcode: 0110011 (7 bits)
2. rd: 00001 (5 bits)
3. funct3: 000 (3 bits)
4. rs1: 00010 (5 bits)
5. rs2: 00011 (5 bits)
6. funct7: 0000000 (7 bits)

So the machine code would be 0x003100B3