RISC-V Newsletter - September 2024

Welcome to the new RISC-V International newsletter, where you can discover the latest from the RISC–V? community, including news, events, technical developments, and training opportunities!

News

• Brazil is making significant strides in developing artificial intelligence (AI) infrastructure, focusing primarily on High-Performance Computing (HPC), semiconductor technology, and large language models (LLMs). Learn more about how Brazil is fostering innovation through collaboration and open standards.
• RISC-V International launches a new AI web page that brings together the latest talks, news stories, and ecosystem companies. The RISC-V ISA is a common language for the development of AI systems, enabling a software-based approach to hardware which unleashes a new level of compute and algorithm innovation, along with a better business case for bringing these new ideas to market. Learn more in Wevolver’s latest article, RISC-V Enables Performant and Flexible AI and ML Compute.
• RISC-V International introduces the newly elected RISC-V Board of Directors Officers and Members.

Discover the latest industry news on the RISC-V news page.?

Events

• Join us at the RISC-V Summit North America 2024! Connect with industry leaders, explore cutting-edge developments in AI/ML, security, automotive, data centers, and beyond. Don’t miss out on this chance to network, learn, and collaborate with the best in the field. View the technical presentations and stay tuned for the full agenda!

??? Register today and take advantage of our Buy 1, Get 1 50% Off BOGO deal—perfect for you and a friend! Secure your spot now and be part of the innovation revolution.

• The 4th RISC-V Summit China 2024 was successfully held in Hangzhou from August 21st to 23rd. This summit brought together over 100 key enterprises and research institutions, approximately 3,000 in-person participants, and more than 20 co-events.

Technical Development

Recently Ratified Specifications

• Double Trap: a double trap occurs when a second exception or interrupt happens while the system is still handling a previous trap, leading to critical errors and loss of data, which is especially challenging during the early phase of trap handling. The ISA Double Trap Extensions, Ssdbltrp and Smdbltrp, are designed to address these issues by enabling critical error handling across different privilege modes. You can find the ratified specification here.

Specifications in Public Review

• RVA23/RVB23 Profiles: the RVA23 profile standardizes 64-bit RISC-V application processors for broad software compatibility, while RVB23 targets customized 64-bit processors, focusing on flexibility for specialized OS builds.
• Privileged Specification 1.13: the Machine-Level ISA and Supervisor-Level ISA (Version 1.13) chapters in the Privileged Architecture ISA Manual (Volume II) detail the RISC-V privileged architecture, including the instructions and functionalities necessary for operating systems and external device support.
• Nexus-based Trace (N-Trace), Trace Control Interface and Trace Connectors: RISC-V N-Trace is based on the IEEE-5001 Nexus Standard and provides a complete trace system for RISC-V cores, enabling detailed program flow tracking and debugging across SoC/MCU designs. The Trace Control Interface Specification defines the trace control interface and the Trace Connectors, outlines connectors for external trace probes.

You can follow the progress of the extensions development here.

Training?

• Featured Work: Microarchitecture Security: The Spectre Affair?
• < Come Hack With Us @ Summit North America />?
• Become an official RISC-V Advocate

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Quick Links:

• Access the latest advancements and technical discussions on the RISC-V International YouTube channel
• For comprehensive updates and industry news, visit the RISC-V News page
• Explore membership opportunities with RISC-V International to actively participate in our community