RISC-V Newsletter - November 2024

Welcome to the new RISC-V International newsletter, where you can discover the latest from the RISC–V? community, including news, events, technical developments, and training opportunities!

Thank you to everyone who attended RISC-V Summit North America 2024! Attendees from over 400 organizations brought incredible energy to the event, connecting and engaging with the latest advancements across the RISC-V ecosystem. The Summit featured various presentations across focus areas like AI/ML, HPC/Data Center, Automotive, Software, Security, and ISA and Design Tools, showcasing RISC-V’s growing influence across multiple industries.

Key highlights of the Summit included three impactful side events—RISC-V 101, the Hackathon, and the Google Collaboration Breakfast. Each brought together a mix of industry newcomers and seasoned experts, sparking meaningful networking and hands-on learning. These gatherings were a testament to the RISC-V community’s dedication to collaboration and pushing boundaries, creating another valuable step forward toward an open, flexible computing future.

Attendees left with fresh insights and stronger industry connections, reaffirming the Summit’s role as a key event for driving computing forward. Session recordings are available to stream on the RISC-V International YouTube channel!

News

• RISC-V Announces Ratification of the RVA23 Profile Standard: RISC-V International announced that the RVA23 Profile is now ratified. Vector and Hypervisor extensions are key mandatory components of the RVA23 Profile, addressing math-intensive workloads including AI/ML & cryptography, and enterprise hardware, operating systems, and software workload

• Chile’s First Steps with RISC-V: Paving the Way for Technological Innovation: Chile is embarking on an exciting journey into the world of RISC-V. As the country takes its initial steps with RISC-V, there is growing enthusiasm and a wealth of opportunities to harness this technology for national development, education, and economic growth

• Highlights from the RISC-V Summit 2024

• Nvidia to ship a billion of RISC-V cores in 2024

Technical Development

RVA23 and RVB23 are now ratified!

- RVA23 Profile: aimed at enhancing software portability across 64-bit RISC-V application processors, RVA23 sets a unified standard for operating system compatibility, essential for broad software adoption without vendor lock-in. Key features include the Vector and Hypervisor extensions, boosting performance in AI/ML, cryptography, and cloud computing

- RVB23 Profile: this profile offers a flexible approach for custom 64-bit processors, allowing hardware implementers to tailor processors for specialized applications without being bound to a strict binary interface

Priv 1.13

- The RISC-V Privileged ISA Version 1.13 brings new functionality and enhancements to the RISC-V ecosystem, particularly at the machine and supervisor levels. These updates include more comprehensive error management, refined control over machine state registers, and improved performance monitoring, especially in virtualized environments

Pointer Masking

- "Pointer Masking" in RISC-V allows CPUs to ignore upper address bits for tagging, enabling efficient memory safety checks, like those in HWASAN, with reduced overheads and enhanced security across privilege modes

Training

• Watch the Hackathon presentations from the RISC-V Summit
• Interested in mentoring the next generation of RISC-V Engineers? Propose a project by December 1st for Spring projects! Become a mentor today!

Quick Links:

• Access the latest advancements and technical discussions on the RISC-V International YouTube channel
• For comprehensive updates and industry news, visit the RISC-V News page

Explore membership opportunities with RISC-V International to actively participate in our community