RISC-V Newsletter - February 2025

Welcome to the new RISC-V International newsletter, where you can discover the latest from the RISC–V?community, including news, events, technical developments, and training opportunities!

News

• RISC-V at Embedded World 2025: Innovation, Networking & Must-See Sessions: The RISC-V Pavilion is back at Embedded World 2025! Visit us in Hall 5, Stand 5-119 for hands-on demos, expert talks, networking events, and exciting giveaways—plus, don’t miss our exclusive conference sessions on March 12.
• How NVIDIA Shipped One Billion RISC-V Cores In 2024: At the recent RISC-V North America summit, NVIDIA’s Vice President of Multimedia Architecture, Frans Sijstermans gave his insight into why NVIDIA chose RISC-V as the architecture for its embedded microcontrollers and how it has become an important part of enabling their product success.
• RISC-V HPC excitement at Supercomputing 2024 sets up an unmissable ISC 2025: The RISC-V HPC community is gaining momentum, tackling performance and sustainability challenges with open, flexible architectures. Check out our latest blog recapping the successful RISC-V events at SC24 and learn how you can get involved at ISC25—submissions are open until March 16
• What’s on Tap From RISC-V in 2025?: RISC-V is advancing with the new RVA23 Profile, ensuring software compatibility while retaining flexibility. In this interview, Andrea Gallo discusses RISC-V’s growing role in AI, HPC, and automotive, emphasizing hardware-software co-design as the key to future innovation.

Events

• RISC-V Summit Europe Registration is now OPEN! Join us in Paris, France from May 12 - 15, 2025. View the event schedule and side events.

• RISC-V at Embedded World - March 11 - 13 in Nuremberg, Germany. Visit the the RISC-V Pavilion in Hall 5, Booth 5-119. Our sponsors, Andes Technology, DeepComputing, Semidynamics, Siemens, and SiFive will be giving presentations in the RISC-V Pavillion. The “powered by RISC-V” sessions take place on March 12 discussing RISC-V Development Ecosystem and RISC-V System Design. For more information, contact [email protected].
• Early bird registration and content submission is OPEN for the RISC-V in Space workshop taking place in Gothenburg, Sweden - April 2-3, 2025.

Technical Development

Specifications

The RISC-V community continues to advance with 4 newly ratified specifications, enhancing efficiency, interoperability, and debugging capabilities across diverse applications:

• Zilsd & Zclsd extensions optimize RV32 load/store operations using register pairs. Zilsd (32-bit) and Zclsd (16-bit compressed) reuse RV64 encodings, improving code density and performance. They enforce aligned even-odd registers, support atomic memory access, and allow stack-pointer relative operations.
• Server SoC Specification standardizes server-class SoC requirements for portability and compatibility in OS, hypervisors, and firmware. It defines clocks, timers, interrupt controllers, IOMMU, PCIe subsystems, RAS, QoS, security, and performance monitoring. Key components include ACPI, PCIe root complexes, IMSIC for MSIs, and a mandatory IOMMU for DMA security. It ensures hardware standardization, security, and efficient resource management for server computing.
• Debug Specification v1.0 defines a standardized debug architecture for hardware and software debugging. It introduces the Debug Module (DM) for halt, resume, and single-step control, supports memory and register access, and enables triggers for breakpoints and watchpoints. It includes JTAG-based Debug Transport Module (DTM) and system bus access (SBA). Security features such as authentication and restricted debug modes ensure protection. The design is modular, scalable, and supports multi-hart debugging, facilitating efficient low-level debugging.
• Semihosting Specification v1.0 enables applications running in a debug/simulation environment to interact with the host system (console, file system, time, etc.). It is based on ARM Semihosting but defines a RISC-V-specific binary interface using a special EBREAK instruction sequence. Parameters are passed through general-purpose registers (a0 for operation, a1 for parameters). This approach minimizes infrastructure needs for debugging and system diagnostics.
• Technical Session: The RISC-V Technical Session (Feb 20, 2025) explored Transformer acceleration using the PULP cluster, featuring 8 RISC-V cores, a 24×8 RedMulE-based systolic GEMM accelerator, and SoftEx, a novel unit for softmax and GELU. It addresses non-linearity bottlenecks in Transformer workloads. Watch here: YouTube.

Training?

Calling RISC-V Member Organizations: Expand Mentorship Opportunities!?

Mentoring is a win-win! By offering mentorship opportunities in the RISC-V ecosystem, you’re not only helping grow your future team and fast-track your project but also ensuring RISC-V’s long-term success.?

With hundreds of applicants this Spring and only a handful of available spots, your support is more critical than ever. Think of this as your chance to ensure RISC-V’s growth!

Why Become a RISC-V Mentor?

? We handle all logistics, so you focus on mentoring

? You get access to highly qualified, eager mentees

? RISC-V International covers the stipend and supports you throughout the onboarding/mentorship process

Together, we can meet the increasing demand for hands-on real-life work experience. Propose your mentorship project today!

Did you know that you can now showcase your work in our Learn Repository on GitHub?

We are continuously amazed by the innovative projects you’re working on, and we wanted to give you a platform to showcase them!?

Maybe you will find future collaborators or an organization interested in working with you. ?? Share your RISC-V projects here!?

Quick Links:

• Access the latest advancements and technical discussions on the RISC-V International YouTube channel
• For comprehensive updates and industry news, visit the RISC-V News page
• Explore membership opportunities with RISC-V International to actively participate in our community