RISC-V Newsletter- December 2024

Welcome to the new RISC-V International newsletter, where you can discover the latest from the RISC–V?community, including news, events, technical developments, and training opportunities!

As 2024 comes to an end, the progress within the RISC-V ecosystem stands out as truly remarkable. This year has been defined by significant breakthroughs in AI, automotive, and IoT, reshaping the computing landscape. Industry milestones, innovative partnerships, and a strong collaborative community have driven advancements that continue to set new standards. The momentum achieved throughout 2024 highlights the transformative impact of open standards and global cooperation, paving the way for future innovation.

News

• Celebrate five key moments from 2024 that set the stage for an even better 2025?
• RISC-V Summit returns to Europe in 2025, taking place in Paris on May 12-15, 2025?
• How RISC-V standards are changing the world [Q&A]
• RISC-V for HPC at SC24
• Interview with Calista Redmond, CEO, RISC-V International

Discover the latest industry news on the RISC-V news page.??

Events

• Sponsor the RISC-V Pavillion at embedded world 2025 - only 5 premier slots left! Contact [email protected] for more information - other opportunities include a speaking slot, video interview, private meeting spaces within the pavilion.
• RISC-V Summit Europe is set to take place in Paris on May 12-15, 2025. More details to be announced soon.

Technical Development

A Look Back at the RISC-V Specifications Ratified in 2024

In 2024, the RISC-V advanced significantly with a series of ratified specifications that enhance debugging, security, performance, and system integration. Here’s a concise overview of the newly ratified specs:

Debug & Trace Improvements

• Nexus-based Trace (N-Trace): standardizes a Nexus-like trace interface for detailed execution visibility, improving debugging, validation, and performance tuning.
• Control Transfer Records (CTR): defines a standard format for recording branches, jumps, and exceptions, enabling easier reconstruction of execution paths for debugging tools.
• E-Trace Encapsulation: encapsulates trace data in a standardized format to ensure interoperability with existing tools and simplify post-silicon analysis.

System-Level Enhancements

• ACPI Functional Fixed Hardware (FFH): introduces ACPI support on RISC-V, streamlining platform configuration and power management in servers and complex systems.
• Supervisor Binary Interface 2.0: efines the interface between RISC-V firmware and operating systems, enhancing portability, maintainability, and feature support.
• Supervisor Counter Delegation: allows supervisors to delegate performance monitoring capabilities for improved flexibility and resource control.

Privileged Specification 1.13

Updates the privileged architecture, strengthening virtualization, memory management, and OS-level functionality.

RVA23 & RVB23 Profiles

Defines platform profiles to ensure baseline feature sets, improve interoperability, and streamline compliance testing.

Architectural & ISA Extensions

• Brain Float 16 (BFloat16): adds native BFloat16 support, boosting AI/ML performance and energy efficiency.
• Pointer Masking (J): masks pointer bits to enhance security against memory corruption attacks.
• May-Be-Operations: introduces conditional execution semantics for more flexible and compact code generation.
• Byte and Halfword Atomic Ops: supports smaller atomic operations for finer-grained concurrency control.
• A Extension Components and B Extension Components: refines atomic (A) and bit-manipulation (B) extensions, ensuring clarity, optional features, and forward compatibility.
• Indirect CSR Access: provides indirect methods to access Control and Status Registers, reducing complexity and improving portability.

RAS & QoS Enhancements

• Quality-of-Service Identifiers: standardizes QoS tags, enabling prioritized resource allocation and better performance predictability.
• RAS Error Record Interface (RERI): defines a uniform way to log hardware errors, aiding in fault diagnosis and system reliability.
• Capacity/Bandwidth QoS Register Interface (CBQRI): offers registers for fine-grained capacity and bandwidth management, improving resource utilization in multi-tenant systems.

Control & Security Mechanisms

• Shadow Stacks & Landing Pads: strengthens return address integrity and call targets to mitigate control-flow attacks.
• Resumable Non-maskable Interrupts: ensures safe handling and resumption of critical interrupts, supporting fault-tolerant and safety-critical systems.
• Double Trap: clarifies nested trap behavior, improving system stability during complex exception handling.
• Obviating M-Management Instructions: reduces overhead in memory-management operations by removing unnecessary instructions once PTEs are valid.

As the RISC-V ecosystem expands into data centers, AI workloads, and embedded systems, these standards ensure developers, implementers, and users benefit from a stable, interoperable, and forward-looking platform, and to further support the community, several new activities have begun to evolve: a Proof of Concept for using the Vale linting tool to guide spec writers in style and language improvements, fostering clearer and more consistent documentation across the organization; implementation of the dependabot tool on GitHub, enabling automated updates to docs-resources submodules for streamlined adoption of theme, font, and other style changes; and progress toward creating a web-based library of all RVI specifications and supporting documentation to help the broader community easily find the materials needed to learn about and contribute to the RISC-V ecosystem.

Training?

• Join 2024 Mentees in sharing the details of their Mentorship Project on January 15, 2025. Register and details here.
• MIT Reality Hack, supported by RISC-V, invites you to join the action at a hands-on hardware hackathon, January 23-27!

Quick Links:

• Access the latest advancements and technical discussions on the RISC-V International YouTube channel
• For comprehensive updates and industry news, visit the RISC-V News page
• Explore membership opportunities with RISC-V International to actively participate in our community