Relation between clock skew and frequency of operation
Ankit Mahajan
Senior Physical Design Engineer | Qualcomm | Ex-HCL | APR | LEC | Amateur Blogger | VITian |
Let's take a simple scenario in which two related flops, flop A and flop B are there. The combinational cloud delay is assumed to be 2ns, Tclk->q is 0.5ns. The setup and hold requirement for the flop is 0.1ns and 0.2ns, respectively. The scenario is shown in the figure below.
What is the maximum frequency (minimum clock period) at which this circuit is able to operate properly? Let's dig deeper into this. For a design to work as intended at a certain frequency, both hold and setup requirements should be met.
Both the above conditions should meet for the circuit to work as intended. In the figure above Tskew = 0. Let's consider the setup equation first. It can be seen that the minimum clock period should be 2.6ns for the design to operate as intended. Hold requirement will be met as arrival time (2.5ns) is greater than the hold time (0.2ns).
Now let's see how adding skew impacts this design and the operating frequency. Add a positive skew of 1ns in the above design. The new situation will look like this.
It can be seen that the Tclk is reduced from 2.6ns in earlier case to 1.6ns in the second case. Hold requirement is also meeting. It means that by adding a positive skew, the circuit can be made to operate at higher frequency. Isn't it amazing to add positive skew and make circuit work faster?
Let's take it one step further and see how the circuit behaves. Let's add a positive skew of 3ns in the above design and see how the dynamics of the circuit change.
Adding too much of positive skew will lead to hold violation. Time period of the clock cannot be negative, minimum it can be 0 which also means that the frequency is infinite which is meaningless. Setup will meet at any value of frequency but hold violations will occur in the design, so the design won't operate as intended.
Note: The skew used in the above circuit is also called useful skew which can be used to fix timing paths in the full design by tweaking the clock (pushing or pulling the clock)
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Let me know if anything else can be added to this post and if any discrepancy is observed, feel free to correct me.