Reason why build phase is Top down in UVM

Build phase and Final phase are the phases in UVM phasing mechanism which are executed in top down fashion and rest all the phases follows the bottom up approach.

Lets look at the class hierarchy structure of uvm phasing mechanism first.

As we can observe from the above diagram that the complete phasing mechanism is subdivided into 3 phases: uvm_topdown_phase, uvm_bottomup_phase and uvm_task_phase.

Simple class declaration of all these phases a are shown below:-

virtual class uvm_topdown_phase extends uvm_phase 

and then

class uvm_build_phase extends uvm_topdown_phase 

Similarly for uvm_bottomup_phase

virtual class uvm_bottomup_phase extends uvm_phase 

and the syntax for declaration is similar for uvm_task_phase as well.

Now coming on to question:-

Why build phase is top down:-

Generally when we are building a testbench in uvm if we look at the hierarchy we will find at the top there is something called as tb_top or top module which is the static part of the testbench.

The following snippet of code is provided for better understanding:-

module tb_top(); 
//DUT Instance 
//Interface Instance 
//Clock generation 
 
initial 
  begin 
   //Virtual Interface Instance 
//Code you will write 
....... 
....... 
run_test(); 
end 
endmodule 

So when run_test is called from the top module it initiates uvm phasing mechanism which in turn called uvm_test and it executes the build phase of the test class.The build phase of test in turn called the environment and then environment is going to call the agent and so on.Basically the child class can not inherit the properties or it can not be built until the upper level components in the hierarchy wouldn’t get created.

The build phase has to be constructed first so that the top level components has to be built before moving down to the next level of hierarchy as we can consider our phase phasing structure as an acyclic graph.

The final phase is also top down since all the testcases and the stimulus related procedures ends here and it is the final stage before exit.Hence it is being used to check for the final adjustment or loopback is needed or not before exit.

Rest other phases are bottom up phases,take the example of connect phase,it is basically used for TLM interconnection between the components and generally its needed to move up the hierarchy as the connections are mostly port to port,port to export and export to export.

The other bottom up phases like end of elaboration,start of simulation etc are mainly used for printing topology,tweaking of the environment,accessing configuration information and this can only be possible in hierarchial fashion in bottom up only after build phase finish its execution.

**This article is orginally published by me on my Quora profile**