Ralf’s GaN & SiC News (September 21, 2023)
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Ralf’s GaN & SiC News (September 21, 2023)

Welcome to the latest edition of my newsletter on and. If you want to contribute to it, please reach out to me via [email protected]


Miscellaneous News


Vanguard International Semiconductor: The Future of GaN & SiC

From left to right: John Wei, Maurizio Di Paolo Emilio and Shyh-Chiang Shen
From left to right: John Wei, Maurizio Di Paolo Emilio and Shyh-Chiang Shen

In an exclusive interview with Maurizio Di Paolo Emilio of Power Electronics News , John Wei, President of Vanguard International Semiconductor Corporation (VIS) (VIS), and Shyh-Chiang Shen , GaN program director at VIS and professor at the Georgia Institute of Technology in Atlanta, provided a broad overview of the wide-bandgap semiconductors. Here are some of the key points.

Concerns Using SiC & GaN

According to Wei and Shen, the conservative stance is rooted in several factors. First, power electronics require new packaging technologies to accommodate the increased power-handling capabilities of GaN and SiC devices. This resistance to change stems from the industry’s hesitance to shift from existing packaging solutions. However, recent advancements in heatsink technology are gradually changing this landscape.

Second, concerns about defect density in GaN and SiC persist. Despite the presence of defects in GaN, its wider bandgap mitigates its impact on device performance. SiC, though not without defects, still outperforms silicon-based devices in many aspects. Derating GaN devices to account for defects has become common practice, ensuring reliability.

GaN for Higher Voltages

Epitaxial growth remains a significant challenge in GaN and SiC production. The choice of substrates, such as silicon or sapphire, plays a pivotal role. GaN-on-silicon leverages existing infrastructure but is limited in voltage-handling capacity, typically up to 650 V. In contrast, the GaN-on-QST substrate from Qromis, Inc. allows for thicker epitaxial layers, enabling higher-voltage applications, potentially up to 1,200?V or higher.

With its thicker epilayers, GaN-on-QST can handle much higher voltages up to 1,200?V or even 2,200?V, making it suitable for high-voltage applications. According to Wei and Shen, the device built on GaN-on-QST can achieve up to 2.2?kV of breakdown voltage; for 1.2-kV applications, the devices would preferably need a 50% breakdown voltage overhead, i.e., 1.8?kV.

Manufacturing GaN-on-silicon devices at higher voltage ratings necessitates advances in fabrication techniques and materials. Questions arise regarding wafer size, uniformity, and yield. If the manufacturing process is not optimized and results in low yields or prohibitively high costs, the technology may not be commercially viable. Another factor to consider is the intense competition in the power electronics market, especially in the 650-V range. SiC is a well-established competitor. For GaN-on-silicon to thrive at 1,200 V, it must offer distinct advantages over SiC and have a clear path to market adoption.

Due to the extant silicon manufacturing infrastructure, GaN-on-silicon is preferred in many situations, Wei and Shen said. This, however, restricts the substrate’s thickness and thus its use in low- and medium-voltage applications, with 650?V being the maximum observed.

Migration from 6- to 8-inch and then to 12-inch wafers

During the fabrication of GaN-on-silicon substrates, substrate fracturing poses the greatest difficulty. Despite using sturdier silicon substrates, companies are still contending with breakage issues, leading to a search for alternative substrates. Breakage remains a significant obstacle, influencing the production and dependability of GaN devices.

Regarding scalability and cost-effectiveness, the transition to larger wafer diameters (e.g., 8-inch and 12-inch) is viewed as productively advantageous. Nonetheless, this transition presents its own set of obstacles, including the management of stress and the adaptation of existing technologies and toolkits. Companies transitioning from 6-inch to 8-inch wafers may encounter issues with material quality, tool compatibility, and the need to develop new processes.


Silicon Diffusion in AlN

AlN and Al-rich AlGaN are attractive candidates for deep-UV optoelectronic and high-power and RF electronic devices thanks to their wide bandgap, high breakdown field, high saturation velocity, high thermal conductivity, and resistance to harsh environmental conditions. One of the main challenges in the development of AlN applications is to obtain efficient p-type and n-type doping.

In this study, Valeria Bonito Oliva and her team from Leibniz-Institut für Kristallzüchtung , Ferdinand-Braun-Institut, Leibniz-Institut für H?chstfrequenztechnik , IM2NP CNRS UMR 7334 , and Universit?t Münster describe the diffusion behavior of silicon in bulk AlN with low dislocation density. They experimentally study the diffusion of Si donors to provide fundamental diffusion parameters and to get insights into the defects or defect complexes involved in the diffusion process. This is key to understanding doping and compensation in AlN. This study could potentially open new perspectives for n-type doping in AlN by Si diffusion.

Valeria Bonito Oliva , Dominique Mangelinck , Sylvia Hagedorn, Hartmut Bracht , Klaus Irmscher, Carsten Hartmann , Philippe vennéguès , Martin Albrecht; Silicon diffusion in AlN. J. Appl. Phys. 7 September 2023; 134 (9): 095103. https://doi.org/10.1063/5.0159641

Gallium Nitride News


GaN Valley and International Semiconductor Executive Summits Join Forces

from left to right: Marnix Tack (CTO BelGaN), Jubel Miah (I.S.E.S.), Alan Zhen Zhou (CEO BelGaN)
from left to right: Marnix Tack (CTO BelGaN), Jubel Miah (I.S.E.S.), Alan Zhen Zhou (CEO BelGaN)

Recognizing the increasing importance of GaN technologies for the transition to a lower energy-consuming society and sustainable future, GaN Valley and International Semiconductor Industry Group (I.S.E.S.) are joining forces to give their members the best possible opportunity for and access to knowledge exchange, collaborations, education, research projects and events focused on GaN innovation and growth.

The I.S.E.S. Power EU 2024 summit set for September 2024 in Italy, will welcome the GaN Valley as the exclusive co-host for the GaN-focused day of the summit. Drawing from its knowledge, network, and experience, the GaN Valley will be able to provide a premium contribution to an interesting and valuable day.

I.S.E.S. will be joining the GaN Valley flag event in the spring of 2024, where parties from along the European GaN supply chain will share their latest insights, research, and innovations as well as work together on- or launch jointed projects.

Members from both networks will benefit from the collaboration by gaining access, either free or at a discount, to the activities of the other party. This will be kicking off with I.S.E.S. members getting access to the member-only (online) seminars of GaN Valley.

Besides this, the partners will join forces to share the latest insights on GaN developments and market research, as well as promote the GaN field and its innovations on an international and regional level, ensuring the accessibility of knowledge and expertise to those interested in, and ready for adopting new power solutions.


EPC Achieves Power Density of 5130 W/in3 with a Bi-Directional LLC Reference Design

EPC - Efficient Power Conversion announces the availability of the EPC9159, a 48 V / 12 V, LLC converter designed for high-density 48 V server power and DC-DC converters. This reference design can deliver 1 kW of power in a 17.5 mm x 22.8 mm footprint for a power density of 5130 W/cm3. This is achieved by employing GaN power switches operating at high switching frequencies in both the primary and secondary circuits.

The power supply topology used in the design of the EPC9159 is based on the LLC topology. The implemented LLC consists of a primary side full bridge, a fixed ratio planar transformer, and a center tab synchronous rectifier for the secondary side. The primary full bridge uses four EPC2619, 80 V-rated 3.3 m? GaN transistors, and the secondary uses six EPC2067, 40 V-rated 1.3 m? GaN transistors.

The EPC9159 achieves a power stage efficiency of 98% at 25 A and a full-load efficiency of 96.2% at 83 A into 12 V. This design is ideal for high-density computing applications such as artificial intelligence and advanced gaming.

“The EPC9159 is the ideal solution to address the growing power needs of artificial intelligence and to support the transition to 48 V input for the new high-density and high-efficiency servers required for these advanced computing applications,” added Alex Lidow , CEO of EPC.

GaNSafe to Smash the Glass Ceiling

“There has been a glass ceiling into data center, into solar, and into electric vehicles,” says Stephen Oliver , of Corporate Marketing & Investor Relations at Navitas Semiconductor . He told Compound Semiconductor Magazine & CS International Conference that while the company’s previous products excelled in efficiency, reliability, and quality, they didn't meet all the needs for lengthy operation at high powers. “The GaNsafe range breaks through, smashes that glass ceiling, and can now be taken seriously by customers in the high-power areas.”

To enable higher power operation, GaNsafe features refinements to both the IC and its packaging. The three key advances at the chip level are: the introduction of a Miller clamp; a more intelligent approach to handling short-circuits, as well as ensuring overcurrent protection; and an absence of overshoot and undershoot during switching.

Since the start of this year, about 40 of Navitas’ customers have been working with products from the GaNSafe portfolio. These firms include Enphase Energy , a producer of power inverters for the solar industry; and 吉利控股集团 , a maker of power systems for the electric vehicle (EV) market that supplies its products to Volvo Group ’s EV off-shoot Polestar , as well as Proton and Lotus Cars Europe .


IQE announces strategic collaboration with VisIC Technologies

IQE has announced a strategic collaboration with VisIC Technologies Ltd. to develop the highest reliability d-mode GaN power products for use in electric vehicles inverters. These devices will be processed on 200mm (8”) epiwafers that will be developed at IQE's UK facilities, leveraging its well-established expertise in GaN technology.

VisIC’s D3GaN technology (Direct Drive D-Mode GaN) promises to reduce power consumption, increase reliability, and enhance performance in electric vehicles. By combining VisIC Technologies' innovative device solutions with IQE's epitaxy excellence, this partnership aims to accelerate the adoption of GaN-on-Silicon technology in EVs, significantly contributing to the evolution of sustainable transportation.

“Together, we are poised to create a brighter and greener future for transportation. The cooperation brings higher availability of ground-breaking technology for GaN-on-Silicon and paves the way for a resilient supply chain to serve the automotive industry,” said Dr. Tamara Baksht , CEO and Co-Founder of VisIC Technologies.

Silicon Carbide News


SiC Module from Vincotech Helps AMZ Racing to Break World Record

The electric racecar “mythen” set a new world record for the acceleration of an electric car on September 1, 2023. The vehicle accelerated from zero to 100 km/h in 0.956 seconds within a distance of 12.3 meters. The car was developed by students and alumni of the Swiss universities 瑞士苏黎世联邦理工学院 and HSLU Hochschule Luzern at AMZ Racing . Vincotech has contributed to this with its Wolfspeed -powered SiC modules.


GE Research: A Superior Process for the SiC Superjunction

Schematic view (left) and scanning electron microscopy, cross-sectional view (right) of GE’s 4.5kV SiC charge-balanced (CB) MOSFET. These switches implement epitaxial regrowth and high-energy implantation similar to SJ devices.
Schematic view (left) and scanning electron microscopy, cross-sectional view (right) of GE’s 4.5kV SiC charge-balanced (CB) MOSFET. These switches implement epitaxial regrowth and high-energy implantation similar to SJ devices.

A formidable challenge for SiC unipolar devices arises because at blocking voltages of 3.3 kV or more, these switches and diodes suffer from high conduction losses at elevated temperatures, while SiC bipolar devices, such as IGBTs, exhibit a prohibitive high forward-voltage drop of 3 V. Therefore, in these systems, the advantages of SiC technology over that of the silicon IGBT are diminished.

One solution that’s attracted interest is the SiC superjunction. This architecture breaks the unipolar conduction limit and offers an improved trade-off between the specific on-resistance and the blocking voltage in medium-voltage-class applications.

In Compound Semiconductor Magazine & CS International Conference , Reza Ghandi from GE全球研发中心 reports a novel fabrication architecture for producing devices operating above 3.3 kV, based on ultra-high-energy implantation and epitaxial growth. The researcher developed a superjunction intermediate charge-balanced technology. This involved the implementation of a novel drift layer architecture, to create buried charge-balanced p-type regions, which are electrically connected to the top body contact through mega-electron-volt, high-energy implanted regions.

This is an attractive alternative to the multi-epitaxial and trench-refill approaches to making superjunction devices, and it offers a scalable solution towards the realization of medium-voltage-class, high-frequency, solid-state switches.


The Global Silicon Carbide Investment Race

Global announced or planned compound semiconductor fab investments (source: ATREG)
Global announced or planned compound semiconductor fab investments (source: ATREG)

Chip makers around the world are highly attentive to the size transition of SiC substrates. With Wolfspeed being the first to activate production capacity for eight-inch, other suppliers are aggressively following suit.

“By our calculations so far, we at ATREG, Inc. estimate current SiC fab investments to amount to close to $14 billion worldwide and that is only the beginning,” shares Stephen Rothrock , founder and CEO of ATREG. “With its new John Palmour materials facility in NC, Wolfspeed will multiply its current SiC capacity by 10, with capex investments as a percentage of revenue of 100%. These numbers are staggering.”

“In the 25 years ATREG has been tracking the global semiconductor manufacturing asset market, we have never seen any new technology ramp up so quickly. Despite the downturn our industry is currently experiencing, we are witnessing a very strong upside in SiC. With SiC power devices, major IDMs the world over are seeing an opportunity to grow,” Stephen Rothrock.

Could silicon carbide become the victim of its own success over time?

“We could draw a comparison with what happened with sapphire for blue LEDs whereby a reduction in average selling price could likely happen,” says Jean-Christophe ELOY , President and Founder of Yole Group . “At the time, the price of sapphire decreased dramatically with the significant capacity add-up by Chinese players in the mid-2010. It accelerated the penetration of LEDs in displays and lighting due to competitive prices and device accessibility. When it comes to SiC, the ecosystem will need to deal with the discrepancy of demand/supply and quality.”


Wolfspeed Featured at 50 Leaders of Change

Wolfspeed is featured in the 50 Leaders of Change documentary series of Global Thought Leaders . Wolfspeed produces more than 60% of the world’s silicon carbide – and it’s investing in the future of the material with two new planned facilities announced in the past year alone. They were the first company to figure out how to commercialize silicon carbide as a group of graduate students at 美国北卡罗莱纳州立大学 .

Since its inception in 1987, the company has made more than 90% of the silicon carbide in the world. They’ve also paved the way in easing supply chain constraints with the introduction of 200 mm wafers, translating to 70% more semiconductor chips per wafer. It’s not the end of the road though, in the works are three new R&D facilities with strategic partners to focus on next-generation power semiconductors that harness the power of silicon carbide even further.

Watch this video featuring co-founder John Edmond, CTO Elif Balkas , and CEO Gregg Lowe .


Plasma Polishing SiC Offers a Sustainable, Lower Cost Alternative to CMP

Figure 1: A visual representation comparing Plasma Polish and CMP for pre-epi substrate preparation
A visual representation comparing Plasma Polish and CMP for pre-epi substrate preparation (Source: Oxford Instruments)

As SiC demand ramps up, the focus on the supply side is increasing. Future cost reduction in SiC processing may involve plasma polishing SiC wafers at several stages of the device fabrication flow, as an alternative or complementary process, to traditional chemical-mechanical polishing (CMP).

Advantages of Plasma Polish over CMP

  • Plasma Polish removes sub-surface defects which CMP may not be as efficient at removing. Defect inspection and electrical results shown later help to corroborate this. This can improve yield and hence reduce the die cost.
  • As CMP has a mechanical component to it, it is more prone to wafer breakage and scratching. Further, it can create stress on the wafer that can lead to problems in subsequent Fab process steps.
  • Plasma Polish offers a lower Cost of Ownership (CoO) direct plug-in polishing alternative in the Fab process line. Oxford Instruments plc has estimated 30,000 – 150,000 liters of slurry material is saved per CMP tool per year. CMP is a water-intensive process. Costs of the polishing pads, slurry, water, and the disposal of the effluent all add up to be significantly higher than the operational cost of running a Plasma Polish tool. Although the initial capital cost of Plasma Polish can be higher, a 60% reduction in total cost of ownership is estimated for 150 mm wafers, with a significantly higher CoO reduction expected for 200 mm wafers.
  • Not-contact Plasma Polish is more easily scalable to larger wafer sizes.
  • A reduced environmental footprint is estimated with Plasma Polish – CMP consumes lots of clean water and requires toxic chemical effluent disposal. The exhaust gas handling for Plasma Polish falls within the normal requirements of other etch tools in the Fab.
  • Non-uniformity in the growth process necessitates current 200 mm SiC wafers to be thicker (~ 500?μm) than the 350 μm thickness typically seen with 150 mm wafers. Thinning this down may be possible over time and be part of a cost reduction approach (i.e., increasing the number of wafers/boule). In this scenario, the Plasma Polish process should be more capable of handling thinner wafers, while the mechanical aspect of CMP will require careful tuning to reduce the risk of wafer breakage.

The Plasma Polish process from Oxford Instruments can be part of a broader set of solutions to the challenges of bringing down costs with SiC. The company has made significant progress with their customers in qualifying Plasma Polish on their substrates, with improvements in both upstream and downstream processes, bringing substrate cost and technical benefits for the entire manufacturing process.


Toshiba: Industry’s First 2200 V Dual SiC MOSFET Module

Toshiba Electronic Devices & Storage Corporation has developed the MG250YD2YMS3, the industry’s first 2200 V dual SiC MOSFET module for industrial equipment. The new module has a drain current rating of 250 A and uses the company’s third-generation SiC MOSFET chips. It is suitable for applications that use DC voltages of 1500 V, such as photovoltaic power systems and energy storage systems. Volume shipments have already started. Toshiba Electronics Europe GmbH



Thank you for including our ATREG, Inc. / Yole Group #siliconcarbide article in your newsletter, Ralf! Much appreciated!

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