Ralf’s GaN & SiC News (March 7, 2024)
Welcome to the latest edition of my newsletter on Silicon Carbide and Gallium Nitride. If you want to get covered, please reach out to me via [email protected]
Gallium Nitride News
YESvGaN to present vertical GaN-on-Silicon Trench MOSFETs at GaN Marathon
YESvGaN - Wide bandgap power at silicon cost has announced that the first fully vertical GaN-on-Silicon Trench MOSFETs are finished. They demonstrate the feasibility of their vertical GaN membrane transistor concept for large active areas up to 16 mm2. Be sure to attend this year’s GaN Marathon to be the first to learn about the electrical results.
Investigation of atomic layer deposition methods of Al?O? on n-GaN
In this work from researchers of Ferdinand-Braun-Institut, Leibniz-Institut für H?chstfrequenztechnik , Universiteit Gent , and SENTECH Instruments GmbH , three atomic layer deposition (ALD) approaches are used to deposit an Al2O3 gate insulator on n-GaN for application in vertical GaN power switches: thermal ALD (ThALD), plasma-enhanced ALD (PEALD), and their stacked combination. The latter is a novel method to yield the most ideal insulating layer. Also, the influence of an in situ NH? or H? plasma pre-treatment is studied.
Planar MIS capacitors are used to investigate the electrical properties and robustness of the gate insulators. In vacuo x-ray photoelectron spectroscopy (XPS) is used to study the changes in chemical composition after every surface treatment. XPS shows that all plasma pre-treatments efficiently remove all carbon contamination from the surface, but only NH3 plasma is observed to additionally remove the native oxide from the n-GaN surface. The water precursor step in the ThALD process does not completely remove the CH? ligands of the trimethylaluminum precursor step, which might electrically be associated with reduced forward bias robustness.
The O? plasma step in the PEALD process is associated with the removal of carbon and a tremendous increase of the O content in the GaN surface region. Electrically, this strongly correlates to an enhanced forward bias robustness and an increased forward bias hysteresis, respectively. The ThALD/PEALD stack method mitigates the shortcomings of both ALD processes while maintaining its advantages. Electrical measurements indicate that the stack method alongside NH3 plasma pretreatment provides the best characteristics in terms of hysteresis, threshold voltage, forward bias robustness, and interface trap density of states.
Liad Tadmor , Sofie Vandenbroucke , Dr. Eldad Bahat Treidel , Enrico Brusaterra , Paul Plate , Nicole Volkmer , Frank Brunner , Christophe Detavernier , Hans-Joachim Würfl , and Oliver Hilt; “Investigation of atomic layer deposition methods of Al?O? on n-GaN”. J. Appl. Phys. 28 February 2024; 135 (8): 085701. https://doi.org/10.1063/5.0189543
Wise-integration and QPT raise fundings
Wise-integration raises €15 Million in Series B funding round to support international growth
Wise-integration ’s Series B round was led by imec.xpand with participation from Supernova Invest , BNP Paribas Développement , Région Sud Investissement (RSI), CREAZUR , CASRA CAPITAL , and ANGELS FOR GREENTECH . The round will fuel mass production and commercial deployment of the company’s flagship products, WiseGan and WiseWare, its digital-control technology, and its support for clients globally as they adopt these solutions. It included the five investors from the previous funding and three new investors.
QPT achieves crowd-funding milestone in under 24 hours
After just a few months for the business, QPT launched this week its crowd-funding campaign on Crowdcube. The company hit its initial funding milestone of ￡600k in under 24 hours! But there are another two weeks to go. You can invest here: https://www.crowdcube.eu/companies/qpt/pitches/qno9gl?country=DE
Temperature-Dependent Thermal Impedance Measurement of GaN-Based HEMTs Using Transient Thermoreflectance
A team of researchers at the 英国布里斯托大学 studied the transient thermal response of GaN HEMTs is studied using transient thermoreflectance (TTR) measurements. The change in the thermal impedance at various ambient temperatures is observed and analyzed using finite-element (FE) simulation and thermal equivalent circuits.
A temperature-dependent Cauer model has been implemented for predicting the transient temperature response of the device under test (DUT), applicable to arbitrary power dissipations or ambient temperatures. This work provides a practical way for determining or verifying transient thermal models of GaN-based HEMTs using RC networks.
郑翔 , James W. Pomeroy, Gautam Jindal and Martin Kuball , "Temperature-Dependent Thermal Impedance Measurement of GaN-Based HEMTs Using Transient Thermoreflectance," in IEEE Transactions on Electron Devices, doi: 10.1109/TED.2024.3367309.
Tagore and Inventchip announce a 500 W GaN power supply with totem-pole PFC
TagoreTech has partnered with InventChip Technology to launch a new compact 500 W power supply reference design with a Totem Pole PFC front-end and an LLC back-end. The reference design incorporates Tagore’s TP44100SG (90 mΩ) and Inventchip’s CCM Totem Pole controller IC IVCC1102/1104 in the front-end PFC section. This high-performance solution is designed for eBikes, adapters, servers, power tool chargers, and communications power supplies. It offers a peak efficiency of 96.7% in this category.
Tagore stated that implementing CCM Totem Pole PFC in a small space is a challenging undertaking. Tagore and Inventchip teams collaborated to create a compact, durable, and cost-effective solution. Tagore team is prepared to assist customers globally in deploying the new CCM Totem Pole PFC solution in a small space by utilizing Tagore’s GaN and Inventchip’s Totem Pole PFC controller.
According to Inventchip, wide bandgap semiconductors, such as GaN and SiC, enable the development of extremely efficient CCM Totem Pole PFC systems. Inventchip’s analog CCM Totem Pole Controllers are now available, offering a small, durable, and cost-effective option for high-volume production.
Silicon Carbide News
TechInsights dive deep into Infineon’s Gen2 SiC MOSFET
Stephen Russell of TechInsights had 英飞凌 ’ second-generation CoolSiC G2 MOSFET in-house. The IMBG120R008M2H with 1200 V/7.7?mΩ was in their labs and under analysis.
The figure of merit that often attracts the most attention for SiC MOSFETs is the specific on-resistance (i.e., the on-resistance normalized to either die or array area). TechInsights’ initial analysis has yielded some interesting results; although they do observe a small reduction in the cell pitch, they see no significant improvement to specific on-resistance for CoolSiC G2. For this device, it is higher than some of the most advanced first-generation M1H products. It is worth remembering that, although important, this metric is not the only way to judge power devices. TechInsights believes that the story of this device is not necessarily raw power density, but rather a refined design focusing on switching behavior and improving robustness.
Why Gen2 seems to be inferior to Gen1
The new CoolSiC G2 devices appear to perform worse across the range of operating temperatures, with a larger spread in MOSFET V(th), R(DS(ON)), and V(SD). Of course, Infineon would not deliberately make an inferior device, so what is going on?
Infineon’s application note AN112138 explains, “CoolSiC Gen2 MOSFETs have slightly worse behavior than CoolSiC Gen1 MOSFETs (across the temperature range); however, this little drawback can be completely ignored due to the reduced switching losses from CoolSiC Gen2 MOSFETs, allowing CoolSiC Gen2 MOSFETs to be still better in efficiency than CoolSiC Gen1 MOSFETs in the target applications. Furthermore, this behavior is the result of a channel improvement. Therefore, the R(DS(ON)) distribution is shifted to the drift region of the device, resulting in an increased process stability leading to a reduction of the required typical to maximum R(DS(ON)) margin in the final datasheets for CoolSiC Gen2 MOSFETs.”
Toward the end of the application note, Infineon also states, “The superior gate oxide allows the use of negative gate driving while the thermal coefficient point lies below 15 V, resulting in a full 15 V capable driving scheme.” TechInsights will be taking a close look at the optimized cell structure in its final analysis with dimensions and dopant wells analyzed in detail.
Indeed, from the datasheets, it seems improvements have been made to the most crucial parameters that impact switching performance such as gate charge and output capacitance. CoolSiC G2 is seen to have significantly lower Q(G) and C(OSS) compared to an M1H equivalent.
Device robustness and confidence in the body diode
Due to the significantly higher current density in a SiC MOSFET (compared to a Si IGBT), having short-circuit robustness has been a challenge for SiC MOSFETs with no manufacturers confidently quoting this until recently. Rohm’s fourth-generation SiC MOSFET range notes a short-circuit withstand time of 4 μs, and the new CoolSiC G2 products now note 2 μs (previous devices did not guarantee a time). There is also now a +200 °C overload temperature noted, truly pushing SiC beyond the capabilities of silicon devices.
In the application note, Infineon also states, “This new-generation technology is ideal for various applications in which a continuous hard commutation on a conducting body diode is present.” This shows a strong belief in the new body diode structure.
TechInsights has launched a full power essentials report on this new CoolSiC generation with process flow analysis to follow.
Amendment
I was contacted by 英飞凌 because some of the findings and conclusions from Stephen Russell in this blog post are not accurate from their point of view. Infineon has promised to send me their perspective for the next newsletter. So stay tuned.
Consortium building for SiC for HORIZON-JU-Chips-2024-2-RIA
Mikael Syv?j?rvi is calling for silicon carbide for HORIZON-JU-Chips-2024-2-RIA (HORIZON-JU-Chips-2024-2-RIA). He is setting up a Zoom meeting (Co-creation Meetup) for March 14, 2024, at 10 AM (Stockholm).
For those interested in this call (and in general interested) to discuss manufacturing and supply chain for Sustainable and greener manufacturing using SiC, there is a meetup to exchange and find opportunities.
Join if you are interested in being part of the SiC supply chain community for future calls and collaborations. If you cannot make it this meeting time, register anyway or send an email and you will be in the loop.
领英推荐
Reliability analysis of planar and symmetrical and asymmetrical trench discrete SiC Power MOSFETs
To further improve the performance of SiC MOSFETs, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This doctoral thesis from Juefei Yang of the 英国布里斯托大学 presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.
Juefei Yang. Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs
YouTube seminar: Electrothermal characterization and reliability of SiC power MOSFETs
With superior properties to conventional silicon power devices, SiC power devices are poised to replace Si power devices in a range of applications like electric vehicles and renewable energies.
Nevertheless, it is important to understand the differences between SiC and silicon power devices. In that sense, electrothermal characterization and reliability studies are fundamental. First, they can help the end user to fully understand the benefits and challenges of using SiC power devices. Second, they can be fundamental for implementing condition monitoring strategies and improving the reliability of SiC-based power electronics.
This YouTube seminar by Jose Ortiz Gonzalez ( 英国华威大学 ) will help the attendees understand the key differences between SiC and silicon devices, providing insight into how to implement condition monitoring and its associated challenges: https://youtu.be/SvgAsmVno9E
Effects of proton implantation into 4H-SiC substrate: Stacking faults in epilayer on the substrate
This study from a team of researchers at Nagoya institute of Technology , 名古屋大学 (Nagoya University), and SHI-ATEX explored proton implantation into 4H-SiC substrates to suppress the expansion of single Shockley stacking faults (SSSFs), which is a source of bipolar degradation in 4H-SiC devices. While previous research has demonstrated the effectiveness of proton implantation in epitaxial layers, concerns about defect generation have persisted.
Therefore, the team implanted protons into 4H-SiC substrates, followed by epitaxial growth. Then, they fabricated PiN diodes using the epitaxial layer aiming to reduce SSSF expansion and enhance PiN diode reliability. The results indicate that proton implantation has no significant suppression effects on the SSSF expansion, coupled with the undesired induction of double Shockley stacking faults. Thus, proton implantation into the substrates does not enhance the reliability of 4H-SiC devices, emphasizing the need for further investigations into suppression mechanisms.
Masashi Kato , Ohga Watanabe, Shunta Harada, Hitoshi Sakane, Effects of proton implantation into 4H-SiC substrate: Stacking faults in epilayer on the substrate, Materials Science in Semiconductor Processing, Volume 175, 2024, 108264, ISSN 1369-8001, https://doi.org/10.1016/j.mssp.2024.108264.
Qorvo Introduces 1200V SiC Modules in Compact E1B Package
Qorvo, Inc. announced four 1200?V SiC modules - two half-bridge and two full-bridge - in a compact E1B package with R(DS(on)) starting at 9.4?m?. These SiC modules are excellent solutions for electric vehicle (EV) charging stations, energy storage, industrial power supplies, and solar power applications.
These SiC modules leverage Qorvo's cascode configuration, which minimizes R(DS(on)) and switching losses to maximize efficiency, especially in soft-switching applications. Silver-sinter die attach reduces thermal resistance to as low as 0.23 K/W; when combined with the stacked die construction found in the “SC” part numbers, power cycling performance is improved by 2X over comparable SiC power modules on the market.
eBook: Adopt SiC with Ease, Speed, and Confidence
Silicon Carbide is an exciting semiconductor technology that is revolutionizing the industry, but integrating any new technology comes with some challenges. Mighty Guides, Inc. interviewed eight industry experts on how Microchip Technology Inc. not only aids engineers in the integration of SiC but also secures their supply chains and helps shape the future of power electronics.
These experts are María Gabriela Ca?ete Cardona ( CIRCE - Centro Tecnológico ), Kasra Latifi Fard ( NanoStructured Coatings Co. ) Tanya Kirilova Gachovska (MDA), Jerome GREGOIRE Chartered Engineer (Ascendance Flight Technologies), Naveed ur Rehman Malik ( Dyson ), Marc Rommerswinkel (Microchip), Sabah V.S. ( Ather Energy ), and Priyanka Yussuf ( 施耐德电气 ).
This ebook can be downloaded for free at Mouser Electronics .
Discovery of loss imbalance in SiC half-bridge power modules
Would you be content with your converter switching losses being 40% higher than anticipated? It is commonly assumed that power semiconductor switching losses are the same for high-side and low-side devices in a half-bridge power module. However, this paper from researchers at AAU Energy ( 丹麦奥尔堡大学 ) reveals that the high-side SiC MOSFET in a medium-voltage power module exhibits over 40% higher switching energy compared to the low-side SiC MOSFET. The loss imbalance is attributed to the parasitic high-side gate capacitance in the power module, which contributes to the equivalent high-side Miller capacitance.
A physics-based switching energy dissipation model is therefore proposed, distinguishing between low-side and high-side switching energy dissipation. Double pulse testing demonstrates that the high-side switching energy dissipation increases by 5?mJ per 2.5?pF increment in equivalent Miller capacitance, aligning closely with the analytically calculated increase of 6?mJ per 2.5?pF. Continuous power module testing shows a 10?K increase in high-side junction temperature. The findings from this paper offer crucial insights into the research, design, and manufacturing of half-bridge modules enabled by SiC MOSFETs.
Benjamin Futtrup Kj?rsgaard , Gao Liu , Thore Stig Aunsborg, Dipen Narendra Dalal, Jannick Kj?r J?rgensen , Bj?rn Rannestad , Hongbo Zhao , and Stig Munk Nielsen , "Discovery of Loss Imbalance in SiC Half-Bridge Power Modules – Analysis and Validations," in IEEE Transactions on Power Electronics, doi: 10.1109/TPEL.2024.3368115.
Miscellaneous News
Experts weigh in on GaN & SiC at APEC 2024
In this video from Maurizio Di Paolo Emilio of Power Electronics News , a lineup of distinguished speakers from semiconductor companies shares insights into groundbreaking developments in GaN- and SiC-based power devices.
The SiC speakers delve into advancements in SiC substrates. They discuss progress made in improving substrate quality and manufacturing techniques to enhance device performance, reduce defects, and boost reliability. Furthermore, they shed light on specific market sectors or applications in which SiC devices are proving advantageous, detailing their companies’ investments in these areas. The speakers include:
The GaN speakers explore the significance of substrate material choice for GaN-based power devices. They elaborate on how this choice impacts device performance, reliability and manufacturability and discuss how researchers are tackling substrate-related challenges. Additionally, the speakers delve into specific market segments where GaN devices are outperforming traditional silicon-based solutions, driving adoption and revealing the technology direction of their respective companies. The speakers include:
Infineon’s Wide-Bandgap Developer Forum
For many years now, 英飞凌 ’s Wide-Bandgap Developer Forum has been an exciting event, bringing together experts from the fields of SiC and GaN. On April 16, 2024, this will take place again. Infineon will be broadcasting specialist presentations live from their studio in Munich. There, also the latest CoolSiC Gen2 will be presented.
The keynote speech by the Division Presidents Dr. Peter Wawer (Green Industrial Power) and Adam White (Power & Sensor Systems) will kick off the event and provide inspiring insights into market developments and our wide-bandgap strategy. Guest speakers are Andy Ma from Anker Innovations , Jian Wang from 上汽集团 E-propulsion group, and Shaoxiong (Victor) Yao from SINEXCEL ESS.
Starting April 16, 2024, 8 am CET / 3 pm SGT, the sessions of the Wide-Bandgap Developer Forum will be available. The sessions are recorded and will be available on demand after the event.
Viewpoint: If GaN is too fast for your application, consider SiC instead
In the world of semiconductor power switches, there is a belief that faster is better. However, fast voltage and current edge rates cause problems. The slightest inductance causes ringing and overshoot. 1?V could be generated from 1?nH at an edge rate of 1?A/ns. It only takes around 1?mm of PCB track to reach this inductance value. If this is the source connection of a GaN HEMT and is common to the gate drive loop, that 1?V spike will be injected into the gate, in opposition to the drive voltage. With the low threshold voltage of GaN being at around 1.5?V, this presents the risk of phantom turn-on and device damage. These issues are well known, and engineers will typically slow down GaN switching rates.
Avnet Silica proposes to use SiC MOSFETs at relatively low frequencies instead of GaN can make sense as dynamic losses are low anyway, especially if a resonant topology is used. In this case, the absence of reverse recovery losses in GaN is also not of value. Both GaN and SiC will have higher and approximately equal body conduction losses in reverse compared with a Si-MOSFET. SiC will also need some effort to slow down and control edge rates – it is still much faster than silicon – but it will be easier to tame.
The voltage limit of around 650?V for GaN is also a practical limitation. Stacked or multilevel arrangements can allow the operation to higher levels, but the cost and complexity spiral. Weigh this against the SiC MOSFET advantages of a simpler and more noise-immune gate drive, a robust avalanche rating, and currently lower cost and better availability, and SiC continues to keep its place as a contender in power conversion applications.
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1 年Amendment: I was contacted by Infineon Technologies because some of the findings and conclusions from Stephen Russell in his blog post about the CoolSiC Gen2 are not accurate from their point of view. Infineon has promised to send me their perspective for the next newsletter. So stay tuned.
Semiconductor Industry Advisor
1 年Thank you Ralf for publishing this report on regular basis ??
Power Electronics Designer @ PowerCon A/S | R&D in Mega-Watt Power Electronics Converters | SiC power semiconductor specialist
1 年Thank you Ralf for sharing our work!