Ralf’s GaN & SiC News (February 20, 2025)
Welcome to the latest edition of my newsletter on silicon carbide, gallium nitride, and other wide bandgap semiconductor materials. If you want to get covered, please reach out to me via [email protected]
Content
Miscellaneous News
Navitas to unveil a new paradigm in power
On a live-streamed event on March 13, Navitas Semiconductor will unveil a breakthrough in power conversion that will create a paradigm shift across multiple major end markets. These developments include both semiconductor and system innovations which are expected to drive major improvements in energy efficiency & power density and further accelerate the adoption of gallium nitride and silicon carbide technologies to displace silicon.
Gene Sheridan (CEO), Dan Kinzer (CTO, COO), and Jason Zhang (VP of Engineering) will uncover this next inflection in power conversion, including technology details, and specific application examples. Also, they will describe the expected market impacts and business opportunities from these innovations.
GaN/SiC cascode device with 3D co-packaging and enhanced dv/dt control capability
To unlock the full fast-switching potential of the GaN-HEMT/SiC-JFET cascode device, parasitic interconnection inductances are minimized with a 3D stacked co-packaging configuration. This configuration offers the benefits of reduced switching loss and suppressed oscillation.
A team at 香港科技大学 proposes to enhance such a 3D co-package configuration with dv/dt control capability of the GaN/SiC cascode device by introducing an additional gate-drain capacitor, C(GD-LV), to the low-voltage GaN HEMT. This additional C(GD-LV) improves the coupling between the input control gate voltage and the JFET's gate voltage, which ultimately determines the switching speed of the GaN/SiC cascode device.
Experimental results verified the GaN/SiC cascode device, when equipped with the 3D co-packaged configuration and the additional C(GD-LV), demonstrated fast switching capability with adequate dv/dt control.
Ji Shu , Jiahui Sun, Mian TAO , yangming du , S. W. Ricky Lee , Kevin J. Chen , (2025). Unlocking the Full Potential of GaN/SiC Cascode Device with 3D Co-packaging and Enhanced dv/dt Control Capability. IEEE Transactions on Power Electronics. PP. 1-9. 10.1109/TPEL.2025.3530510.
Synergies of intelligent power electronics: Unveiling and driving advances with physics-informed AI
The convergence of Artificial Intelligence (AI) and Power Electronics is a catalytic force reshaping our energy landscape. The rapid evolution of AI technology has ignited a technological revolution within power electronics, revolutionizing each stage of the lifecycle—from modeling and design to control and maintenance—ushering in a new dawn in energy management and utilization. While remarkable performance gains have been demonstrated in numerous applications, concerns have surfaced regarding the substantial data prerequisites, computational overheads, and inefficiencies inherent in solely data-driven AI methodologies, impeding their seamless integration into industrial settings. Enter Physics-Informed AI techniques striking a delicate balance between the reliance on intricate physical principles and copious data resources. By infusing foundational physics insights into AI frameworks, these techniques promise enhanced interpretability, diminished data demands, heightened efficiency, and notably superior performance, making them a viable choice for deployment in power electronics applications where computational resources and temporal constraints are paramount.
In this webinar, Hongjian Lin and Yangxiao Xiang from the University of Alberta and Chongqing University will delve into the core tenets of Physics-Informed AI, unveiling innovative approaches to embed well-established physical laws within AI models. We will delve into how these methodologies elevate contemporary power electronics practices across all lifecycle stages, with a particular focus on system modeling, agile control, and intelligible reliability maintenance. By spotlighting the symbiotic interplay between physics and AI, this webinar endeavors to inspire attendees to explore novel methodologies and forge collaborative ventures that can propel the domain of power electronics to unprecedented heights. Join us for a captivating session brimming with invaluable insights, discussions, and networking prospects.
Exploration of p-type conductivity in β-Ga?O? through Se-Mg hyper co-doped: An ion implantation approach
As β-Ga?O? continues to advance, achieving stable p-type doping has become a key research focus. This study from researchers at 香港科技大学 proposes a method to introduce defect energy levels near the conduction band and acceptor doping elements to achieve p-type doped β-Ga?O?.
They utilized ion implantation to achieve co-doped Ga?O? with Se and Mg elements, employing a 50 kV acceleration voltage to reach a peak purity concentration depth. The concentrations of Se and Mg were quantified, with the highest concentrations reaching 2.35 × 1022/cm3 (Se) and 8.99 × 1021/cm3 (Mg), consistent with simulation results. After implantation, the Se-Mg co-doped β-Ga?O? underwent rapid thermal annealing at +850 °C in an oxygen environment to mitigate implantation damage. By adjusting the Se and Mg implantation dose, the team could slightly tune the bandgap from 4.42 to 4.37 eV. Experimental characteristics revealed valence band maximum values and exhibited potential p-type behavior achieved by Se-Mg co-doping. Hall measurements indicated probable p-type conductivity.
However, further verification is required. Additionally, first-principles density functional theory simulations provided calculations of substitutional defect formation energies and Fermi levels within the β-Ga?O? lattice, further elucidating the causes of electronic structure changes induced by doping.
Yimin Liao, Hanzhao Song, Zhigao Xie, Chuang Zhang, Chee-Keong Tan, Exploration of p-type conductivity in β-Ga?O? through Se-Mg hyper co-doped: An ion implantation approach, Materials Today Advances, Volume 25, 2025, 100559, ISSN 2590-0498, https://doi.org/10.1016/j.mtadv.2025.100559.
Gallium oxide JFETs reach beyond 10 kV breakdown voltage
Researchers based in the USA and Japan report the demonstration of more than 10-kV E-mode Ga?O? lateral JFETs with nickel oxide (NiO) reduced-surface-field (RESURF) structures and hybrid-drain, operating up to 250°C [Yuan Qin et al, IEDM, session 25-5, 2024].
The team from Virginia Tech and the Us Naval Research Laboratory in the USA and novel crystal technology in Japan presented their work at the IEEE International Electron Devices Meeting (IEDM 2024) in December. Further, unlike other WBG materials, Ga?O? is available in substrate wafers up to 150 mm (6 inch) in diameter. The crystal material can be grown from a melt.
The epitaxial material was grown on a semi-insulating (010) Ga?O? substrate by molecular beam epitaxy (MBE) with the n-type channel grown on an unintentionally doped (UID) layer. Two samples were produced, #A and #B, differing in the donor n-channel layer thickness (t(d)) of 50 nm and 16 0nm, respectively. A thicker channel should enable lower R(ON).
The threshold voltage (V(TH)) of #A and #B reached up to 1.9V and 1.5V, respectively, enabling E-mode operation. The gate potential was limited by gate leakage to around 3.5–4V. The corresponding specific on-resistances (R(ON,SP)) were 703 mΩ?cm2 and 92 mΩ?cm2. The team writes: “The temperature coefficient of R(ON) is smaller than that reported in a 10kV SiC MOSFET, suggesting a lower conduction loss at high temperatures. The average lateral E-field at BV is 1.75 to 2.45?MV/cm.”
Silicon Carbide News
Wolfspeed: Increasingly American
Wolfspeed believes its survival and eventual success is intimately tied to its ability to improve its balance sheet and financing costs based upon funding from the US government, comments Kevin Matocha in his blog post.
In this article, he strives to provide an assessment of the language changes used over the past several quarters that indicate the company's strategy. Also, he analyzes alternatives to the assessment that Wolfspeed is necessary for national security. Worth reading.
Kevin’s takeaways:
Infineon starts delivering components to customers processed on 200-mm SiC wafers
英飞凌 will release the first products based on 200-mm SiC wafers to customers in Q1/2025. The products were manufactured in Villach, Austria. Additionally, the transition of Infineon's manufacturing site in Kulim, Malaysia, from 150-mm wafers to 200-mm diameter wafers is fully on track. The newly built Module 3 is poised to commence high-volume production aligned with market demand.
Li Auto begins mass production of their proprietary SiC power modules
理想汽车 has started mass production of modules equipped with its SiC power chip in preparation for more BEV models that should be rolled out later in 2025, the company announced on Weibo. The in-house developed and self-produced SiC power modules and next-generation electric drive assemblies have been mass-produced at the company's Suzhou semiconductor production base and Changzhou electric drive production base, respectively, it said.
The company began construction of its SiC chip R&D and production site in August 2022 and said at the time that the site was expected to go into production in 2024. The production base was built by Suzhou Sike Semiconductor, a joint venture between Li Auto and Hunan Sanan Semiconductor , a leading domestic semiconductor company.
A temperature-independent gate-oxide degradation monitoring method for SiC MOSFETs based on turn-off ringing
Gate-oxide degradation in SiC MOSFETs is a significant concern. Consequently, several methods have been developed to monitor the aging degree. In this article, a team from 重庆大学 (Chongqing University) proposes a temperature-independent method for gate-oxide degradation monitoring by measuring the minimum turn-off circuit parasitic inductor voltage v(cir_min) at a specific gate resistor and voltage.
The temperature sensitivity of v(cir_min) is analyzed based on a derived model. Adjustment of the turn-off gate voltage and resistance is proposed to mitigate the impact of temperature on v(cir_min). The devices under test are aged by high-temperature gate bias (HTGB) experiments and are tested in double-pulse tests (DPT). A 32 V bias for 42 h and 25–150 °C temperature results in changes of 6.55% and 0.103% in v(cir_min), respectively.
The experimental results show that the proposed method is effective in maintaining temperature independence. Additionally, the effects of bus voltage, load current, and bond wire failure on v(cir_min) are also tested and analyzed. The proposed method provides a valuable tool for accurately monitoring SiC MOSFET gate-oxide degradation in scenarios characterized by significant temperature fluctuations.
Xinghao Zhou, Pengju Sun, Kaiwei Li, Qingsong Liu, Lan Chen, and Bo Wang. 2025. "A Temperature-Independent Gate-Oxide Degradation Monitoring Method for Silicon Carbide Metal Oxide–Semiconductor Field-Effect Transistors Based on Turn-Off Ringing" Electronics 14, no. 4: 771. https://doi.org/10.3390/electronics14040771
A real-time junction temperature estimating method for SiC MOSFET based on the turn-on drain-source current oscillation
Online junction temperature (T(J)) measurement is critical for SiC MOSFET reliability evaluation health management and life prediction. To make the tradeoff between availability, simplicity, as well as accuracy, this article from researchers at the 华中科技大学 (Huazhong University of Science and Technology) demonstrates a real-time junction temperature estimating method by selecting the current oscillation peak of drain to source (I(osc,peak)) during turn-on transient as a temperature-sensitive electrical parameter (TSEP). The theoretical and simulation analysis results show that the I(osc,peak) is available to be a TSEP. Then, the model of I(osc,peak) and T(J) is derived through a fitting curve based on the experimental results. The voltage and load current dependency of the proposed method are also discussed.
The experimental results demonstrate that the bus voltage level has a negligible influence on the relationship between I(osc,peak) and T(J), the value of I(osc,peak) is increasing with the increment of the current level at the specific temperature. The sensitivity of the proposed method has a satisfactory performance of junction temperature estimation. The estimation circuit of the proposed method has simple hardware with low cost and is easy to implant with the gate drive of SiC MOSFET.
Yang, F., Liang, L., Zhang, Z. (2025). A Real-Time Junction Temperature Estimating Method for SiC MOSFET Based on the Turn-on Drain-Source Current Oscillation. In: Sha, A., Chen, H., Wei, B., Xie, W., Chen, S., Sun, D. (eds) The Proceedings of 2024 International Conference of Electrical, Electronic and Networked Energy Systems. EENES 2024. Lecture Notes in Electrical Engineering, vol 1329. Springer, Singapore. https://doi.org/10.1007/978-981-96-1852-1_25
A quick comparison of SiC solutions across leading manufacturers – Part 2
In a previous article, Stefano Lovati analyzed a selection of discrete SiC power devices in a comparative study based on key electrical properties in their datasheets. This follow-up article will focus on SiC power modules rather than discrete components. Additionally, the analysis will include modules from manufacturers not previously covered, offering a broader and more independent perspective. Only publicly available information from manufacturers’ websites (such as datasheets and application notes) was used. This article covers 英飞凌 , 意法半导体 , ROHM Semiconductor Europe , 安森美半导体 , and Wolfspeed .
Gallium Nitride News
Cambridge GaN Devices closes $32m Series C funding round
Cambridge GaN Devices Ltd (CGD) has successfully closed a $32 million Series C funding round. The investment was led by a strategic investor with participation from British Patient Capital and supported by existing investors Parkwalk Advisors , BGF , Cambridge Innovation Capital (CIC), Foresight Group , and IQ Capital . The funding will enable the company to expand its operations in Cambridge, North America, Taiwan, and Europe, and deliver CGD’s unique value proposition to its growing customer base.
“This funding round marks a pivotal moment for CGD. It validates our technology and vision to revolutionize the power electronics industry with our efficient GaN solutions and make sustainable power electronics possible. We're now poised to accelerate our growth and make a significant impact in reducing energy consumption across multiple sectors. We look forward to collaborating with our strategic investor to penetrate the automotive market," said Dr. Giorgia Longobardi , CEO and Founder of CGD.
Review on gallium in coal and coal waste materials: Exploring strategies for hydrometallurgical metal recovery
Gallium, a critical and strategic material for advanced technologies, is anomalously enriched in certain coal deposits and coal by-products. Recovering gallium from solid residues generated during coal production and utilization can yield economic benefits and positive environmental gains through more efficient waste processing.
This systematic literature review from Ewa Rudnik of AGH University of Krakow focuses on gallium concentrations in coal and its combustion or gasification by-products, modes of occurrence, gallium-hosting phases, and hydrometallurgical recovery methods, including pretreatment procedures that facilitate metal release from inert aluminosilicate minerals. Coal gangue, and especially fly ashes from coal combustion and gasification, are particularly promising due to their higher gallium content and recovery rates, which can exceed 90% under optimal conditions. However, the low concentrations of gallium and the high levels of impurities in the leachates require innovative and selective separation techniques, primarily involving ion exchange and adsorption.
The scientific literature review revealed that coal, bottom ash, and coarse slag have not yet been evaluated for gallium recovery, even though the wastes can contain higher gallium levels than the original material.
Ewa Rudnik. 2024. "Review on Gallium in Coal and Coal Waste Materials: Exploring Strategies for Hydrometallurgical Metal Recovery" Molecules 29, no. 24: 5919. https://doi.org/10.3390/molecules29245919
Next generation of ICeGaN for superior no-load and light-load performance
Cambridge GaN Devices Ltd 's ICeGaN technology aims at enabling widespread adoption of GaN HEMTs in power applications through a monolithic solution that offers an increased V_GS(th) (2.9 V) and a wide on-state gate driving range of 9 V to 20 V. This makes it compatible with industry-standard Si gate-driver ICs and controller ICs.
The first ICeGaN product series (H1) introduced the integrated circuit interface to the gate of a standard enhancement mode 650 V p-GaN HEMT, offering superior flexibility, reliability, and protection features. The interface regulates the internal gate of the p-GaN HEMT to stay within a safe range across different temperatures and includes a Miller clamp transistor which prevents spurious turn-on during high dV/dt events by swiftly grounding the internal pGaN gate when the external gate is turned off. In ICeGaN devices, a V_dd supply powers the IC interface, and it has a finite contribution to the device power consumption dependent on operating conditions.
The second series of ICeGaN products (H2) comprising 55, 130, and 240 mΩ power devices, advances the ICeGaN concept with an intelligent fully integrated NL3 circuit that aims at particularly minimizing the power losses under no-load and light-load conditions. When the external gate is in the off state, the current consumption of the V_dd pin (I_dd) is reduced to near-zero (typical 70 μA) in H2 devices. In the gate on-state, the Idd is reduced by 40% (typ. 1 mA) compared to H1 (typ. 1.7 mA). This work presents the characterization and comparison of the 55 mΩ devices from the H2 and H1 ICeGaN product series.
Kalparupa Mukherjee , Jin Zhang , Kaspars Ledins , Carlos Toyos , Nirmana Perera, Loizos Efthymiou , Sheung Wai Martin Fung , Martin Arnold , Giorgia Longobardi , Florin Udrea, Next Generation of ICeGaN for Superior No Load and Light Load Performance, Power Electronic Devices and Components, 2025, 100084, ISSN 2772-3704, https://doi.org/10.1016/j.pedc.2025.100084.
CoolGaN in Silicon-footprint packages to drive standardization
GaN suppliers have thus far taken different approaches to package types and sizes, leading to fragmentation and the lack of multiple footprint-compatible sources for customers. 英飞凌 addresses this challenge by announcing a 100-V CoolGaN G3 transistor 100 V in RQFN 5x6 package and an 80-V device in RQFN 3.3x3.3 package. Samples will be available in April 2025.
These transistors offer a footprint that, for the first time, allows for easy multi-sourcing strategies and complementary layouts to Silicon-based designs. The new packages in combination with GaN offer a low-resistance connection and low parasitics, enabling high-performance transistor output in a familiar footprint.
“The new devices are compatible with industry-standard silicon MOSFET packages, meeting customer demands for a standardized footprint, easier handling, and faster-time-to-market,” said, Dr. Antoine Jalabert , Product Line Head for mid-voltage GaN at Infineon.
Investigation of current collapse mechanism on AlGaN/GaN power diodes
In this paper, a team of researchers at Université de Lille , Université Claude Bernard Lyon 1 , CNRS , Université Polytechnique Hauts-de-France , and 意法半导体 proposes a methodology for studying the current collapse effects of GaN power diodes and the consequences on the dynamic on-resistance (R_ON).
This study can ultimately be used to model observed trap effects and, thus, improve the equivalent electrical model. Using an in-house circuit and a specific experimental setup, a current-collapse phenomenon inherent to GaN semiconductors is studied on planar 650 V—6 A GaN diodes by applying high voltage stresses over a wide range of temperatures. With this method, useful data on activation energy and capture cross section of electrical defects linked to dynamic R(ON) are extracted. Finally, the origins of such defects are discussed and attributed to carbon-related defects.
Martin Doublet , Nicolas Defrance , Etienne Okada , Loris PACE , Thierry Duquesne, Emilien Bouyssou , Arnaud Yvon , Nadir IDIR , and Jean-Claude De Jaeger. 2023. "Investigation of Current Collapse Mechanism on AlGaN/GaN Power Diodes" Electronics 12, no. 9: 2007. https://doi.org/10.3390/electronics12092007
Advanced measurement methods for high-power GaN HEMTs
The issue of high-power device testing urgently needs to be solved as the power level of the devices under test (DUTs) increases. This work from a team at 浙江大学 and the Northwest Institute of Nuclear Technology proposes advanced measurement methods based on three aspects of “measuring capability, security, and stability” with a focus on the features of high output power, easy self-oscillation in mismatch tests, and safety risk in the measurement system of high-power transistors.
In this paper, the wideband limiter and bias filter network are innovatively introduced to improve the stability and security of the measurement circuit. Meanwhile, the output signal of the DUT is suggested to be measured using a spectrum analyzer before the test to avoid damage to the circuit caused by the possible self-oscillation of the transistor. Moreover, an efficient test system of current parameters and S-parameters is developed, with coaxial fixtures offered to boost the test power capacity and cascade bridges adapted to satisfy the pulse operating conditions.
Finally, based on the improved test methods, a GaN HEMT with a gate width of 400 × 32 μm and a power density of roughly 10 W/mm was tested. A relatively complete I-V curve and an S-parameter curve were obtained, demonstrating the effectiveness and applicability of the improved methods.
Lu-Lu Wang, Wen-Rao Fang, Wen-Hua Huang, Zhi-Qiang Yang, Guang-Jian Deng, Chang-Kun Liu, Juan Zhao; Advanced measurement methods for high-power gallium nitride high electron mobility transistors. Rev. Sci. Instrum. 1 January 2025; 96 (1): 014708. https://doi.org/10.1063/5.0226247
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6 天前Ralf, great as always. Thank you!
Thank you for sharing the latest edition of your newsletter on silicon carbide, gallium nitride, and UWBG semiconductors. It’s always great to stay updated on the exciting advancements and research in these critical technologies. The contributions from leading experts and institutions like Wolfspeed, Infineon, and Cambridge GaN Devices really highlight the ongoing innovation in this space. At SinoGaN, we specialize in high-quality gallium nitride (GaN) epitaxial wafers, which are essential for next-generation power electronics and high-performance devices. Our GaN materials are designed for superior performance in a wide range of applications, and we offer tailored solutions to meet the specific needs of research and industry partners. If you’re looking to source reliable GaN epitaxial wafers or explore potential collaborations, we’d be happy to discuss how SinoGaN can support your efforts in advancing semiconductor technologies.