Race conditions in Verilog
What is wrong with the following Verilog piece of code?
module test(out, in, clk);
input in,clk;
output out;
wire a;
dff dff0(a,in,clk);
dff dff1(out,a,clk);
endmodule
module dff(q,d,clk);
output q;
input d, clk;
reg q;
always @(posedge clk);
q = d;
endmodule
The order of assignments of dff!
Problem: The intermediate node a is set and sampled at the same time.
Solution: use a non-blocking assignment on the flip-flop definition!