QPSK modulation on FPGA

QPSK (Quad Phase Shift Keying) is a technique of RF modulation, mostly used for data transmission and applied with digital systems, often FPGA based, as with most SDR (Software Defined Radio) systems.

I have been developing a QPSK baseband Tx system on a TE0802 board. The main blocks can be seen below, a dummy data generator (data_gen), the modulator itself (qpsk_mod) and a FIR filter implementing the Root Raised Cosine filter (RRC), essential for PSK modulation systems. My custom blocks are created with HLS

After the RRC filter I was interested in the frequency spectrum so I included the XFFT core and another custom HLS IP to convert the complex FFT values into power in log units.

The whole block diagram has a bit more simple elements as well as ILA (Integrated Logic Analyzer) to observe signals:

For the prior mathematical development I used Octave, pretty much like Matlab, but open source and free, and even quite compatible with it, a very useful tool.

The parameters for this example development are:

• Fs: sampling (clock) frequency: 100 MHz
• Fc: carrier frequency: Fs/16 = 6.25 MHz
• Sps: Samples per symbol: 4
• Fsym: Symbol rate: Fs/4 = 25 Msps
• Rb: Bit rate: 2*Fsym = 50 Mb/s

There are a few small variants of QPSK modulation, and I chose the π/4-QPSK where the constellation points are rotated by 45 degrees, with the advantge of transitions not crossing the origin.

Below is a sample of the modulator output, although it doesn't look sinusoidal, this doesn't matter because the baseband still has to be brought to RF with a mixer.

An essential part of QPSK systems is the RRC filter (Root Raised Cosine). It is a matched filter, so there will be another equal filter at the receiver. When applied consecutively (transmitter and receiver) they become equivalent to applying a raised cosine filter. The RRC filter drastically limits the bandwidth used and greatly helps reducing ISI (Inter Symbol Interference). The signal at the RRC filter output looks like this in Octave:

Note that the more sinusoidal-like appearance means less high frequency contents so the bandwidth will be narrower. The RRC filter coefficients are calculated in Octave with the rcosfir function and I include them in a .coe file for the Xilinx FIR compiler to generate a FIR filter.

I added an XFFT block to make a 1024-point fix-point FFT followed by an HLS block that converts the complex numbers into power (the square root of the absolute value) and shows them in logarithmic units (dB) as it is customary.

With Octave I got a result as in the banner of the article, showing a bandwidth of some 30 MHz, quite good as in this exercise the bit rate is 50 Mb/s.

Implementation on FPGA

Even if the TE0802 has a small Zynq Ultrascale+, it has been enough to contain the system and the FFT, RRC filter and power conversion. Note that these 'development' elements use more than half of the DSP available. The ILA also account for a fraction of the BRAM used. A developed system would be much smaller. An alternative to having these in the PL is to use a DMA and bring samples to the software side to perform the FFT in software.

Below is a capture of the signal before and after the RRC filter. Note the 'sharp turns' by the modulator that are 'smoothed' by the filter.

On the output side, below is the frequency spectrum as captured by the ILA, together with the XFFT output (real part). The delay is due to the power calculation by the HLS block. Other than that, regions with high amplitude match the central part of the spectrum with higher power.