Project Machine Extensible: The ISA Rethink

After several failed relationships(with work), learning to drive and cook and genrally being an adult(finally!), yours truly is back at making computers. I made a lot of pointless decisions about my design, but the good one was the ALU.

It seems as if I was "biting more than I could chew" with the super-scalar processing architecture that I discussed in the earlier article. I will now take back all of that and work on a single scalar processor in the "simple" 8-bit design first. Making at super-scalar will be the next project(ProjectMX-SS?).

For the Rethink(IBM reference, if you know) of the system, I have made "several key decisions" regarding the components and architecture. I have decided to retain the original register bank due to its proven efficiency and reliability. This means that I will be removing the additional register bank, also known as the Re-Ordering Buffer (ROB), as it is not necessary for our current requirements and would only add unnecessary complexity to the system.

The Arithmetic Logic Unit (ALU) will remain unchanged, utilizing the same configuration of two cascaded Intel 74181s. It works.

In terms of other components, I have decided to implement register taps. Register taps function similarly to a line decoder but are specifically designed for the entire register bank. They enable access individual registers in all of the places that need that data.

Additionally, I will incorporate register loading codes. These codes allow us to set specific registers to be loaded at designated times, ensuring that data is transferred accurately as per the operational requirements.

Overall, these adjustments aim to simplify the architecture while maintaining the necessary functionality and performance standards. By focusing on essential components and optimizing their use(no idle cycles for the ALU), because RISC and lowspec.

While studying for this project, I greatly benefited from the online computer architecture lectures by David Wentzlaff at Princeton University, Madhu Mutyam at IIT Madras, and the resources available on MIT OpenCourseWare.