Power Conversion with GaN

November 2, 2020 Maurizio Di Paolo Emilio

The GaN technology implemented through its transistors has seen significant improvements until it has reached an optimal cost for Mosfet replacement. All this starting in 2017, where the adoption rate of GaN in 48-Vin DC-DC converters began to take on important connotations in the market. Various topologies, such as multi-phase and multi-level bucks are offering new solutions with greater efficiency to cover the energy demands of the IT and automotive markets. In addition to GaN’s microelectronics, digital control offers an extra boost to improve performance.

“One of the great features of digital control is the ability to reuse common algorithms across application platforms,” said Alex Lidow, CEO at EPC. He continued, “For designers with multiple projects in their future, the investment in going to a digital controller from dedicated analog controllers can be well worth the investment. With digital control it is also straightforward to incorporate multiple communications protocols such as UART, I2C, SPI, and CAN. And, for those designers working in the automotive world, or where bi-directional control is needed, digital control enables dynamic control stability adjustment with automatic gain control including load current reversal. “

In addition to digital control, an important issue when designing with GaN, but in general with electronics, is the qualification test, which provides clear evidence of the strength of the components.

Normal qualification tests for semiconductors involve stressing the devices over an extended period of time or for a certain number of cycles. The objective of qualification tests is to have zero failures on a large group of tested parts.

“At Efficient Power Conversion (EPC) we test parts to the point of failure under every known stress condition. This has given us an understanding of the amount of margin in data sheet limits, but more importantly it has given an understanding of the intrinsic failure mechanisms of our GaN FETs and integrated circuits,” said Lidow.

Digital Control for GaN

Most analog controls suffer from GaN FET compatibility and require additional circuitry to match the gate driver operation. Digital solutions offer a simple and effective way to implement advanced power and temperature protection features in particular. In addition, digital control, such as the dSPIC33CK, makes it easy to dynamically adjust downtime and expand designs from single-phase to multi-phase.

“EPC implemented the dSPIC33CK family for DC-DC projects for several reasons that I can summarize in these points: price, low power consumption, small form factor. Precision control of deadtime with the possibility to preset in increments of 250 ps is particularly important as many customers of eGaN devices work at higher frequencies (e.g., 2 MHz) and are very sensitive to power losses, which are aggravated by the long deadtime required by today’s analog controllers,” said Lidow.

GaN allows you to increase switching frequencies without paying any noise penaltiy. This advantage allows for smaller passive elements in the power stage and faster transient response.

Under these circumstances, the control circuit must be faster. For today’s switching power supplies above 1 MHz, it is necessary to complete sampling and conversion in a few 100ns. The calculation delay must also be in this same range. Modern digital controllers can meet these requirements.

The speed of discrete GaN solutions is undoubtedly faster than silicon equivalents. Using digital control, they can become even more efficient and smaller. Programming, and therefore the associated firmware eliminates many design bottlenecks.

GaN Testing

The stress conditions for most semiconductors concern the testing of parameters such as voltage, current, temperature and humidity, as listed in Table 1.

Table 1: Stress Conditions and Intrinsic Failure Mechanisms for eGaN FETs (Source: EPC)

Test conditions must considerably exceed the limits of the device or board, paying attention to excess conditions that could trigger failures. Alex Lidow highlighted that two types of stress are essential and most worrying for GaN designers: gate-to-source and drain-to-source voltage stress.

Figure 1 shows the failure results of hundreds of devices at various voltages and temperatures translated into a mean time to failure (MTTF). Looking at the graph on the right, with a VGS of 6 V DC you could expect between 10 and 100 parts per million (ppm) failures over 10 years. Lidow shows that the recommended gate drive voltage, however, is 5.25 V and the expected failure rate at this voltage is less than 1 ppm over 10 years.

Figure 1: (Left) mean time to failure (MTTF) for EPC2212 eGaN FETs vs. VGS at both 25 oC and 120 oC. (Right) graph that shows the various probabilities of failure vs. VGS at 25 oC (Source: EPC)

Dynamic resistance (RDS(on)) has been a worrying failure mechanism in early generations of GaN devices. RDS(on) increases when the device is exposed to high drain voltage (VDS) due to strong electron entrapment, and, therefore, more resistance. With the VDS DC voltage at maximum temperature conditions, the electronic candidates for trapping come from the IDSS, which is of the order of uA. To speed up trapping, it is possible to increase the VDS voltage as shown in figure 2.

Figure 2: Data on device failures over time taken at different voltages and temperatures is statistically translated into predictions of failure rates over time, temperature, and voltage

“On the right side of the graph is shown the time for 1 ppm failure (0.0001%), 100 ppm (0.01%), and 10,000 ppM (1%) at various VDSS. At the maximum nominal VDS of this 100 V device, the 1 ppm failure rate is well above the 10-year line,” said Lidow.

The goal of all these tests is to obtain a valid product. Lidow points out that eGaN FET solutions have been documented in over 123 billion hours of device usage in the field, covering the period January 2017 – February 2020, in the main EPC applications in the automotive and telecommunications sector. In total, there were three units of devices that failed.

The main stress conditions described above can be applied continuously as DC polarization, can be cycled on and off, and can be applied as high-speed pulses. Similar current stress conditions can be applied as DC direct current or as pulse current. Also, from the thermal point of view, the stresses can be applied with the same criterion, in this case, by operating the devices at a predetermined extreme temperature for a period of time, or the temperature can be cycled in various ways. The final aim is to obtain a series of failures to be analyzed, defining the mechanisms that led to the failure.  

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