Point of Load (POL) Solutions
Torex Semiconductor Europe Ltd
Power Management IC, DC/DC Converters, Battery Chargers, and Voltage Regulators
For multiple power supply rails for MCU and FPGA
Point of load (POL) converters are a popular choice for applications that require multiple power rails demanded by the latest generation of Microprocessor, DSP or FGPA.? These complex core IC increasingly require sophisticated power schemes and often demand a large number of higher current, low voltage power supply rails.? Providing all the required power supply rails using a multi-channel PMIC means the power must be routed around the PCB from a central point, which can result in poor output regulation and complicated PCB layouts.? Using a PMIC also localises the heat dissipation which can be problematic for thermal management.
These problems can be overcome by deploying several Point of Load (POL) DC/DC Converters instead of a single PMIC, with each DC/DC providing a one supply rail and locating these DC/DC Converter IC close to where the power is required on the PCB.? The resulting shorter PCB track lengths helps to improve VOUT stability and reduces EMI.? The systems heat dissipation can also be spread more evenly around the PCB, which improves thermal management.
Torex specialises in simple, cost-effective, POL DC/DC Converters and this article shows how they can be used in typical applications.
Using Point of Load Micro DC/DC Converters to power a Microprocessor or FPGA
Key System Requirements:
Below is a typical power architecture that meets these key system requirements and which shows how our products can be used in a seamless and efficient POL circuit:
Step-Down DC/DC for MPU/Memory/FPGA as POL
(1) Stable operation, small size and low EMI are realized by placing Micro DC/DC converters with integrated inductors (XCL205/206, XCL211/212) close to the Point of Load (POL) on the PCB. The XCL205/206 and XCL211/212 operate up to 6V and support load currents of 600mA and 2A respectively.? With the XCL205/206 the inductor lies flat on the IC package which shortens the path of the switching current and minimizes noise. For the XCL211/212, the coil is located beside the DC/DC chip which means that both the IC and inductor have good heat dissipation, so large currents can be supported.
RESET IC with Release Delay for Monitoring 5V Input
(2) The XC6119C is a highly precise, low power consumption voltage detector that can operate up to 6V and can detect voltages within a 0.8V~5.0V range. With the built-in delay circuit, connecting the delay capacitance pin to a capacitor enables the IC to provide an arbitrary release delay time. The XC6119C is an ideal choice for monitoring a 5V input and for the start-up / shutdown sequence control and notification of voltage drop to the MPU.
Start-Up/Shutdown Sequence with RC Delay
(3) The RC delay to each CE terminal of the DC/DC and the CL discharge function make it easy to implement start-up / shutdown sequences and the XC6119C can be used to drive the RC delays:
In addition to the specific power rails listed above, the different voltages must be powered on and perhaps more importantly, but often overlooked, powered off, in the correct order to maintain system stability. This is known as “power sequencing” and for start-up will usually begin with the Core voltage and, depending on the FPGA, will end with the I/O voltage. For power off the order is usually the opposite so I/O off first and Core voltage off last. Seems simple enough but there are pitfalls if it isn’t done properly and to do on/off sequencing properly usually means adding a large and expensive capacitor on the Core voltage rail to make sure that it stays on until all the other rails are powered off in the right order during power down.
As mentioned, to have a secure shutdown sequence (power off), the 0.9V Core voltage should be maintained until all the other rails are off, so a large (>2,000μF) and expensive Capacitor is necessary for the Core rail.
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Our solution, however, will enable the sequencing to be done without a PMIC and without the need for a large and expensive Capacitor on the Core voltage rail so a win/win proposal.
Benefit of Point of Load vs. PMIC
The problems with using a PMIC are as follows:
Point of Load Approach
The benefits of the POL proposal are short wiring length by placement of inductor built-in Micro DC/DC in the immediate vicinity of the FPGA. Achieving stable operation and reduction of capacitors and more efficient heat dissipation due to heat source separation. Finally, reduced EMI.
This article is also available on our website and is accessible using the link below.? From the webpage you can link to all the featured products to get more details and download data sheets:
Additional Links:
DC/DC Simulation Tool
DC/DC Measured Electrical Characteristics Comparison Tool