Pizza Masks

What are Pilot Test Chips and Pizza Masks??

Application Specific Integrated Circuits, aka ASIC, are high volume electronic circuits which provide functionality of some portion of communications and/or radar systems. One of major cost components of these ASIC, is semiconductor mask.? Semiconductor masks are used for lithographically fabricating the semiconductor devices onto wafer.? Each wafer requires multiple masks for various layers of fabrications and etching. A typical vanilla CMOS process could easily have 200 masks or more and they could easily cost as much ~$3M depending on the geometry and size of the gates.

Each all layer revisions of ASIC require all ~200 masks; therefore it becomes prohibitively expensive for smaller companies or even big corporations to tape out any design for single project/product.

In order to save cost for any trial of ASIC before design is finalized, it is customary to run some pilot test chips to validate the design as well as the process performances.? For test chips run, it should only be enough number of them to be validated and characterized for desired performances, KPI.

Therefore, many semiconductor fabrications offer Pizza Mask, where number of companies can share the cost for the masks, ~$3M, and get only small portion of wafer area, “pizza”.? Very large corporations typically have their own pizza masks for multiple internal projects, test chips.? Or tandem with another project masks for couple hundred devices.?

Each wafer lot is typically 25 wafers, and small portion of pizza/wafer, can produce few hundred devices per lot, enough to validate design topology and performance metrics.

Augment ORTENGA in your semiconductor device design and developments to utilize cost saving proven techniques which are not only benefits R&D cost, but also improves TTM, hence ROI.