PID in PV Modules

Potential-induced degradation (PID) has received considerable attention in recent years due to its detrimental impact on photovoltaic (PV) module performance in field conditions. Both crystalline silicon (c-Si) and thin-film PV modules are susceptible to PID. While extensive studies have already been conducted in this area, the understanding of the PID phenomena is still incomplete and it remains a major problem in the PV industry.

In grid-connected PV systems, solar panels are typically connected in series to build up the voltage output while the module frames are grounded for safety reasons. Depending on the type of inverter (frequently used transformer-less) used in a PV system, a high electric potential difference between the solar cells and the module frame may be induced in modules at either end of a module string . The electric potential difference causes leakage currents to flow from the module frame to the solar cells (or vice versa, depending on the module position in a module string), which results in PID. This problem will be more severe in the future, as the PV industry is trending towards increasing the maximum system voltage to 1500 V for overall cost reduction purpose.

PID does not occur in grounded systems (Figure 1), where the negative pole of the inverter is grounded, or in systems less than or equal to 600V, which eliminates the high negative voltage potential that drives the PID phenomena.

In the case of an ungrounded system (Figure 2), the PID effect is most severe in the modules with the highest negative potential, which in this case is module 1-.

PID effects are influenced by many factors such as

-         Properties of the solar cell’s antireflective (AR) coating,

-         Encapsulation materials

-         Module construction (e.g., frame or frameless)

-         System topologies.

-         Environmental stress (temperature, humidity, condensation, etc.)

-         Grounding conditions of glass surface (wet or dry),

-         Exposure to light

-         Deposition of soil on the top of module surface

Due to a high electrical potential difference, five leakage current pathways have been identified (In literature) in PV modules. Their relative importance depends on the environmental conditions as well as the packaging materials. Significant progress has been made towards understanding the underlying principles causing the PV efficiency loss due to PID in different types of modules. Whether it is thin-film or c-Si based technologies, sodium ion (Na + ) migration plays a crucial role in the evolution of PID. Electrochemical corrosion of the TCO layer, surface polarization effect and PID-shunting (PID-s), respectively, are three of the most common PID mechanisms in thin-film modules, n-type c-Si modules and standard p-type c-Si modules, respectively. Four types of test methods are available to evaluate the PID susceptibility at both cell and module level. At a module level, chamber PID and Al PID tests are often used, while at a cell level, PID sensitivity can be examined by a corona discharge PID set-up or bias voltage application on a module-like layer stack.

The majority of the PID studies performed so far dealt with standard p-type c-Si modules, as it dominates the present PV market. The progression of PID-s in standard c-Si modules depends on the applied voltage, humidity, and temperature. The leakage current shows an Arrhenius-type relationship with the temperature. Humidity and the applied voltage also affect the PID in multiple ways. Several kinetic models have been proposed to predict PID rates in p-type c-Si modules with meteorological data. Various methods have also been found to effectively prevent PID in p-type c-Si modules. At the cell level, the PID resistance can be improved by:

(1) adjusting the Si/N ratio of the AR coating to a higher value to increase the electrical conductivity;

(2) growing an interlayer (SiO) between the Si and the SiNx  AR coating; and

(3) cleaning the cell surface with energy-rich UV prior to SiNx deposition.

 At the module level, PID can be prevented by using encapsulation materials or/and glass sheets with high bulk resistivity. At the system level, PID-s can be mitigated by ensuring that the active circuit of PV modules is not negatively biased relative to ground or applying a reverse voltage at night. Alternatively, it can be effectively prevented with application of micro-inverters. Moreover, PID-s in p-type c-Si PV modules was found to be reversible; thermal recovery, reverse-biased voltage recovery and a combination of them have been shown to be able to regenerate the PV efficiency loss.