PD-Synthesis (Cont.)

Clock Network Effects

Clock latency,uncertainty,and transition time are few of the clock network effects.

Clock Latency: Latency is the amount of time it takes for the clock signal to be propogated from the original clock source to the sequential elements in the design

Uncertainty: It is the maximum difference between the arrival of clock signals at registers. This is also called skew.The larger the skew, the more difficult it is to meet the timing constraints.

Transition Time: It is the amount of time it takes for a signal to change from logic low to logic high, or from logic high to logic low.

get_clocks command gives the list of clocks defines in the current design

report_clocks command gives the details of the clocks defined in the current design

IO Timing

• Need to specify timing requirements for input and output ports, otherwise DC assumes the signal arrives at input port at time 0 and does not constraint any path that end at output port
• set_input_delay and set_output_delay commands are used to constraint input and output port delays
• The set_input_delay command is used to specify how much time is used by external logic.Dc then calculated how much time is left for internal logic and tries to meet it
• The set_output_delay command is used to specify how much time the external logic needs.DC then calculated how much time is left for internal logic and tries to meet it.

Combinational Delay

• To constraint a purely combinational path set_max_delay and set_min_delay commands are used
• set_max_delay command allows to specify the maximum delay of a timing path, i.e from startpoint to endpoint
• set_min_delay command allows to specify the minimum delay of a timing path

Timing Exceptions

• A false path is a logic path in the design that exists but should not be analysed for timing. A false path is a point-to-point timing exception that removes all timing constraints from a path,which prevents errors from being reported but does not stop delay calculation.

Area

• DC will perform minimal area optimization unless an area contraint is set. Area can be set using set_max_area command. Most cases have a zero max area constraint, in this case DC tries to achieve the best possible area with the impact on run time

Compile

• The process of optimization is done through compile .Optimization consists of three steps- Architectural,Logic Level,Gate level