PCIe Equalization phases

Sampath VP Sampath VP

Sampath VP

ASIC/FPGA Design Professional | SoC Architecture | Technology Evangelist | IEEE Reviewer|

发布日期: 2024年5月30日
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Equalization is a critical aspect of PCIe technology that ensures the integrity of data transmission in increasingly high-speed environments.

As PCIe continues to evolve, we can expect even more innovative equalization techniques to further enhance performance and reliability in future generations of hardware. Phase 0 is the first phase of link equalization. This phase starts when the downstream port sends desired transmitter preset values for each lane to the upstream device. After receiving the downstream port's request, the upstream port increases the data rate of the link to Gen 3 data rate and begins transmitting training sequences back to the downstream port using the desired presets.

Link equalization moves to phase 1 once the connection with Gen 3 is achieved. In phase 1, identical training sequences are sent repeatedly to ensure the correct presets are received, despite the possibility of poor link quality. This is done in order to optimize the link enough to be able to exchange training sequences and complete the remaining link equalization phases for fine tuning.

In phase 2 and 3, link equalization conducts fine tuning on the link. This further optimizes the preset values for the upstream port. Then, in phase 3, same optimization happens for the downstream ports.

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·???????? Phase 0 is where the upstream port starts the equalization process. The link should maintain a minimum speed of 8 GTps to enter the equalization process.If the link is not at 8 GTps but aims to upgrade to this speed, it enters Phase 0 with an EC (Equalization Control) value of 00.Phase 0 involves the exchange of Tx preset and Rx Hint values to adjust transmitter settings. If the data rate changes, the downstream port goes to Phase 1, while the upstream port stays in Phase 0.If the upstream port receives two consecutive TS1s and achieves a BER (Bit Error Rate) of < 10^-4, it moves to Phase 1.Phase 1 involves the exchange of Full Swing (FS) and Low Frequency (LF) information between link partners. The receiver calculates and requests the next set of transmitter coefficients based on this information.If the DSP (Downstream Port) and USP (Upstream Port) Rx detect consecutive TS1s and are satisfied with signal quality, they both move to EC = 10b.If the required signal quality is achieved in this phase, the link sets EC to 00b and exits the equalization process.

PCIe equalization plays a crucial role in ensuring high-speed and reliable data transfer in PCIe-based systems. It enhances signal integrity, enables faster data rates, extends transmission distances, promotes interoperability, and provides flexibility to adapt to different channel conditions. These advantages contribute to the overall performance and efficiency of modern computing systems.

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