PCIe Enumeration

PCIe enumeration is the process of detecting the devices connected to the PCIe bus. switches and endpoint devices are allocated memory from the PCIe slave address space of the HOST.

Enumeration includes the below activities:

Initialization of BAR address of endpoint and switches

Allocation and initialization of MSI/MSI-X addresses for the devices.

Enables bus-mastering capabilities of the device to initiate transactions on the bus.

?Initialization of different capabilities of the devices like power-management, max-payload size, etc

To be precise PCIe has mainly 4 types of transactions

Configuration Transactions

Memory Transactions

I/O Transactions

Message Transactions

PCIe enumeration is performed using?configuration transactions?after PCIe linkup.

BAR address is one of the important part of enumeration for a PCIe device. A PCIe endpoint device will accept any incoming memory transactions only if the address of the incoming TLP matches with BAR address programmed as part of enumeration. So, basically without enumeration PCIe device cannot accept any Memory Transactions, but it can accept configuration transactions as these are part of enumeration itself.

Prerequisites that needs to be satisfied:

a) Root complex is on the Bus 0 and configuration space access of the root complex is accessible using embedded CPU (via API or known mechanism)

b) The EP device that implements a function must have a Vendor ID that is not all '0xF's

c) link training has completed and link has been established on both the sides of the link and the Data link layer is in DL_ACTIVE state.

Enumeration Procedure:

1.???RC driver steps through the hierarchy to find all the connected downstream devices by looping the bus number. For E.g. read the vendor ID of the downstream device for bus 1 and device 0, function 0. If there is valid function implemented on this downstream device, it must return a valid vendor ID and it is first step to discover this device. The config address of Vendor ID is ′h0.

2.???If the device is found, now the device needs to be assigned the memory window so that it gets allocated the memory space on the system memory map. This is done by scanning the BAR's and check for the BAR size and do the allocation accordingly. Downstream device BAR size can be found by writing all one's to the respective BAR register and checking for the bits that are zero's. Root complex driver needs to only set here the base address of the requested memory size.

?After the base address is assigned EP device needs to be configured to enable as bus master so that it can start sending memory TLP requests. Set the command register to enable Bus master, memory enable and IO enable.

In a Switch topology RC iterates from Bus number 0 - 255. For each bus, device number gets iterated from 0 - 31 , for each device searches for function number from 0 - 7.For each valid vendor ID, RC performs the above 3 steps to make the device ready to operation.