PCI Bus Stands for What? Basic and Extension

Peripheral Component Interconnect?(PCI)?is the most widely used hard interface in computers, and almost all motherboard products have this kind of slots with the largest number. The PCI bus is a tree structure, independent of the CPU bus, and can operate in parallel with the CPU bus. PCI devices and PCI bridges can be connected to the PCI bus. And only one PCI master device is allowed, and the others are PCI slave devices, and memory read write can only be performed between master and slave devices, at the same time, the data exchange needs to be transferred through the master device.

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PCI Features

The structure of the PCI bus

As a local bus of the processor system, the main purpose of the PCI bus is to connect external devices, instead of connecting Cache and main memory?in computer.

PCI has many advantages, compared with ISA, EISA and MAC:

(1) PCI bus space is isolated from the processor.

Use the HOST main bridge to distinguish the PCI bus space and the memory space, and the communication between them?needs to convert the address through the HOST main bridge.

(2) PCI is scalable

The HOST main bridge can be used as the root, and then the PCI bridge can be separated, and more devices can be connected to it; but on a PCI bus tree, only 256 PCI devices (including PCI bridges) can be connected at most.

(3) Dynamic configuration mechanism

The addresses used by PCI?devices?can be dynamically assigned by system software as needed.

(4) Bus bandwidth, PCIe is faster

(5) Shared bus mechanism

After the PCI device obtains bus control through arbitration, it will perform data transmission on the bus. The PCI bus arbiter is outside the scope defined by the PCI bus specification and is not necessarily part of the HOST bridge and PCI bridge. This mechanism of occupying the bus is not as good as the switching structure adopted by the PCIe bus.

(6) Interrupt mechanism

Devices on the PCI bus can submit interrupt requests to the processor through four interrupt request signals INTA ~ D#.

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The Structure of PCI

HOST Bridge

The main function is to isolate the memory domain of the processor system from the PCI?bus domain of the processor system, manage the PCI bus domain, and do?the data exchange between the processor and the PCI device. When a PCI device accesses the main memory through the HOST bridge, it needs to perform coherent operation with the processor's Cache, so it is necessary to pay attention on it. In a processor system, each HOST bridge manages a PCI bus tree, and all PCI devices on the same bus tree belong to the same domain.

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Peripheral Component Interconnect

PCI Devices

A PCI master device, a slave device, and a bridge device may have multiple PCI buses in a tree. Among them, the PCI slave device can only passively receive read write requests from the HOST bridge or other PCI devices, but the PCI master device can use the PCI bus through bus arbitration, and actively initiate memory read write?requests?to other PCI devices or the main memory. The main function of the bridge device is to manage the downstream PCI bus and forward bus tasks between the upstream and downstream buses.

HOST Processor

The PCI bus stipulates that at the same time, there is only one HOST processor in a PCI bus tree, which?can initiate a PCI bus configuration request bus transaction through the HOST main bridge, and configure devices and bridges on the PCI bus.

In the PCI bus, the HOST processor is a relatively vague concept. In the SMP (symmetric multiprocessing), all CPUs can access the PCI bus tree under it through the HOST bridge, and these CPUs can all serve as HOST processors. However, it should be noted that the actual manager of the PCI bus tree is the HOST?bridge, not the HOST processor.

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The PCI Bus Load

Table 1: Relationship between PCI Bus Frequency, Bandwidth and Load

The higher the line frequency, the less load that can be connected.

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Signal Definition of the PCI Bus

The PCI bus can be?shared.?Multiple PCI devices can be connected to one PCI bus through a series of signals, which are composed of address/data signals, control signals, arbitration signals, interrupt signals and other signals.

The PCI bus can use a clock frequency of 33MHz or 66MHz, while the PCI-X bus can use a clock frequency of 133MHz, 266MHz, or 533MHz.

Except for signals such as RST#, INTA ~ D#, PME# and CLKRUN#, most of the signals are using?CLK signal for synchronization. Among them, RST# is a reset signal, and INTA-D# signals for interrupt requests.

1. Address and data signals

(1) AD[31:0] signal

The PCI bus multiplexes address and data signals. The first clock transmits the address, and then transmits the data, supporting burst transmission.

(2) PAR signal

It?is the parity signal of AD[31:0] and C/BE[3:0].

(3) C/BE[3∶0] # signal

2. Interface control signals

(1) FRAME# signal

This signal indicates the begin?and the end of a PCI bus transaction. And high level signal is?invalid.

(2) IRDY# signal

If the current PCI bus transaction is write, it means that the data is already valid on AD[31: 0]; if it is read, it means that the PCI target device is ready to receive the buffer, and can send data to AD[31: 0] superior.

(3) TRDY# signal

If the current PCI bus transaction is write, it means that the target device is ready to receive the buffer, and the data on AD[31: 0] can be written into the target device; if it is read, it means that the data required by the PCI device is already in AD[31 : Valid on 0].

(4) STOP# signal

When this signal is active, it indicates that the target device requests the master device to stop the current PCI bus transaction.

(5) IDSEL signal

The PCI bus uses this signal to select the PCI target device when performing configuration read and write bus transactions.

(6) DEVSEL# signal

When this signal is valid, it indicates that the target device on the PCI bus is ready. The difference between this signal and the TRDY# signal is that it?is valid only to indicate that the target device has completed address decoding. In other words, you can?use this signal to notify the PCI master device that its access object is on the current PCI bus, but it does not mean that the target device can exchange data with the master device. However, the TRDY# signal indicates that the data is valid, and the PCI master device can write or read data from the target device.

The PCI bus specification divides PCI devices into three types: fast, medium and slow according to the decoding speed.?Be careful, there is also a negative decoding device on the PCI bus.?When the fast, medium and slow devices cannot respond to the address of the PCI bus transaction, the negative decoding device will?receive the PCI bus transaction?passively. If there is no device accessed by the PCI master device?to set valid DEVSEL# signal,?Master Abort cycle can be used to end the current bus transaction.

(7) LOCK# signal

The PCI master device can use this signal to lock a certain memory or I/O resource of the target device to prohibit other PCI master devices from accessing until the master device that unlocked the resource. And the PCI bus uses it?to implement LOCK bus transactions, in addition,?only the HOST bridge, PCI bridge or other bridges can use the LOCK# signal.

3. Arbitration signal

In a PCI bus tree, each PCI bus has a bus arbiter. A processor system can use a PCI bridge to expand a new PCI bus, which?also needs a independent?bus arbiter?(usually integrated in the PCI bridge). Most HOST bridges also integrate one. When the PCI master device uses the PCI bus for data transmission, it needs to set a valid REQ# signal first, and send a bus request to the bus arbiter. When it?allows the PCI master device to obtain the right to use the PCI bus, a valid?GNT# signal?will be set?and sent to the designated PCI master, and the PCI master device can set the FRAME# signal to be effective and communicate with the PCI slave device?after get the access right.

4. Interrupt request?signals

PCI bus provides INTA#, INTB#, INTC# and INTD# four interrupt request signals. Setting a low?signal?indicates that an interrupt is requested to the processor, and after the processor finishes executing, the interrupt signal is set to high.

The PCI bus stipulates that single-function devices can only use INTA# signals, while multi-function devices can only use INTB# / C# / D# signals. Various errors will inevitably occur during the data transfer process, so the PCI bus provides some error signals, such as PERR# and SERR# signals. Among them, when the PERR# signal is valid, it means that there is a parity error in the data transmission process (except for the special cycle period); and when the SERR# signal is valid, it means that there are three possible errors in the current processor system, which are address/data parity error checking in the special?cycle, and also other serious errors in the system. If the PCI bus supports 64-bit mode, AD[63: 32], C/BE[7: 4], REQ64, ACK64 and PAR64 signals also needed.

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Read and Write Bus Transactions

The basic task of the bus is to implement data transfer, to transfer a set of data from one device to another. The PCI bus supports the following types of memory read write bus transactions.

(1) The HOST processor reads and writes data to the BAR space of the PCI device, and the BAR space can use memory or I/O decoding. The HOST processor uses PCI bus memory read write transactions and I/O read write transactions to access the BAR space of the PCI device.

(2) Data transfer between PCI devices. Two devices on the PCI bus can communicate directly, such as a PCI device can access the BAR space of another device. However, this data transfer is less used in PC processor systems.

(3) The PCI device reads and writes the main memory, that is, the DMA read write operation. It?commonly used in all processor systems, and?is?also the focus of PCI bus data transmission. In most cases, an interrupt will be generated after the DMA read write operation completed. PCI devices can use INTA#, INTB#, INTC# and INTD# signals to submit interrupt requests, and can also use the MSI mechanism to submit interrupt requests.

1. Timing

The control signals related to PCI bus transactions include FRAME#, IRDY#, TRDY#, DEVSEL# and other signals.

When a PCI device needs to use the PCI bus, it first sends a request REQ#, and returns a GNT# signal through arbitration. After the PCI device obtains the control right, FRAME# is set to be valid, and the FRAME# signal will be set to be invalid?when the bus transaction ended. The PCI master device drives the accessed destination address and bus command to AD[31: 0] and C/BE# signals respectively. If the current bus command is to configure read and write, then the IDSEL signal line is also asserted. When the IRDY#, TRDY# and DEVSEL# signals are all valid, the bus transaction will use the data cycle for data transfer. When the IRDY# and TRDY# signals are not valid at the same time, the PCI bus cannot transmit data, and uses these two signals for transmission control.

2. Posted?and?Non-Posted

The PCI bus specifies two types of data transmission methods: Posted and Non-Posted.

The Posted way?means that when the PCI master device transmits data to the PCI target device, when the data arrives at the PCI bridge, the PCI bridge takes over the bus transaction from the upstream bus and forwards it to the downstream bus. With this data transmission method, the PCI bus can end the current bus transaction before the data reaches the final destination, thus solving the congestion problem of the PCI bus to a certain extent.

The Non-Posted way?refers to a data transfer mode in which the current bus transaction can only be ended after the data reaches the final destination when the PCI master device transmits data to the PCI target device. It?will cause certain congestion, so the PCI bus uses Delayed bus transactions to process Non-Posted data requests.

The PCI bus stipulates that only memory write requests (including memory write and invalidation requests) can use the Posted way; while memory read requests, I/O read and write requests, and configuration read and write requests can only use the Non-Posted way.

Illustrate the posted request according to Figure 1

Device 11 needs to perform DMA operation to write data to DDR, then it will first send a request to PCI bridge x1, and bridge 1 will release the control of x1 bus after receiving it, at this time, 11 and 12 can communicate normally. Similarly, bridge x1 will pass the request to HOST main bridge x, and main bridge x will pass the request to the controller. This step-by-step release of bus resources makes the utilization of the PCI bus higher. When non-posted data requests pass through the PCI bus, the bus resources will not be released in time, thus affecting the efficiency and transmission bandwidth to some extent.

3. HOST processor accesses PCI devices

The addresses that PCI devices can directly use are?the PCI bus domains, while the addresses that the processor can directly use are?the memory domains.

Let me talk about the communication steps between the processor and the device 11:

In fact, the processor writes data into the register, first accesses the memory domain address, converts the address into a PCI address through the HOST?bridge,?and?sends the transaction to the PCI bridge x1, and x1 releases the bus. The following process is the same, and finally the PCI device 11 receives the write bus transaction through address decoding.

4. PCI device reads and writes main memory

According to 3?above.

5. Delayed transmission method

Optimize the Non-Posted?way mainly.

The PCI-X bus upgrades the Delayed bus transaction to a Split bus transaction. Because?retry operations of the HOST / PCI bridge can be effectively resolved by using the Split bus transaction. The basic idea of the Split is that first sends the Non-Posted bus request to the receiver, and then it?actively passes the data to the sender.

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PCI Bus Interrupt Mechanism

The PCI bus uses the INTA#, INTB#, INTC#, and INTD# signals to send interrupt requests to the processor.

1. The connection relationship between the interrupt signal and the interrupt controller:

In the topology shown in Figure 1-5, the INTA#, INTB#, and INTC# signals of PCI slots A, B, and C will be connected to the IRQW#, IRQX#, and IRQY# signals of the interrupt controller in a distributed manner, while the INTD # signals will share an IRQZ# signal. When this connection mode is adopted, the load of the interrupt request signal used by the entire processor system is relatively balanced. Moreover,?it is useful to?ensure that the INTA# signal of each slot corresponds to an independent IRQx# signal, thereby improving the efficiency of the interrupt request of the PCI slot.

2. The connection relationship between the interrupt signal and the PCI bus:

Mapping relationship between PCI device INTx# signal and PCI bus INTx# signal

3. Synchronization of interrupt requests

The problem encountered by the interrupt, such as the last data transfer of the DMA to the destination, is also generated at this time, and the interrupt directly acts on the processor, but it is very likely that the data has not been transferred to the destination. Here?the solution is, after the transmission is completely over, send an interrupt signal to the processor, which takes up resources. Another is that after the DMA transfer is completed, the processor requests a certain type of signal from the memory. And it?represents the end signal, which is more convenient.

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PCI-X?Bus

The PCI-X still uses parallel bus method. Most of the bus transactions used by the PCI-X bus are based on the PCI bus, but there are slight differences in implementation details. The PCI-X bus increases the operating frequency to 533MHz, and introduces the PME (power management event) mechanism?first. In addition, it?has also proposed many new features.

1. Split bus transaction

Instead of the delay bus, it improves the transmission efficiency of Non-Posted bus transactions.

Compared with the Delayed bus transaction, the data obtained by the Requester is actively transmitted by the Completer after it?has completely prepared the data, instead of being obtained by the Requester through multiple retries, so the usage efficiency of the PCI-X bus can be improved. And Split bus transactions proposed by the PCI-X bus are inherited by the PCIe bus.

2. Bus transmission protocol

The PCI-X bus changes the transfer protocol used by the PCI bus. The target device can latch the command sent by the master device, and then perform the decoding operation in the next clock cycle. Compared with the PCI bus transaction, the method adopted by the PCI-X bus can effectively increase the operating frequency, although one more clock cycle is used in the bus timing.

Because the master device needs a certain delay to send commands to the target device through the data line. If the frequency of the PCI bus is high, it is difficult for the target device to receive the bus command within one clock cycle and complete the decoding work at the same time. And if the target device can first latch the command sent by the master device, and then decode it in the next clock cycle, it can effectively solve the problem of insufficient margin in the decoding time, thereby increasing the frequency of the PCI-X bus.

3. Block-based burst transfer

In the PCI bus, the data sending end knows how many bytes of data need to be sent, but the receiving end doesn’t. This uncertainty brings great challenges to buffer management at the receiving end. For this reason, the PCI-X bus uses a data block-based burst transmission method. The sending end sends data to the receiving end in units of ADB (allowable disconnect boundary), and a burst of reading and writing is over?one unit. In this way, the receiving end can predict in advance whether there is enough receiving buffer from the sending end, so that the current bus cycle can be disconnected in time to save the bandwidth.

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