PCB Routing on Layer Two - Breaking the Steadfast Rule
It was about five years ago when Intel gave up Trails and Wells for Lakes as the project names for the 64-bit computing devices. Up to that point, Intel embraced a package design philosophy they called “via-channel”. The pin-pitch was still fairly generous while rows of balls would be strategically depopulated so that there was just enough empty space for fan-out.
Pins around the outer edge of the device are the most precious when it comes to ball-mapping.
It was about five years ago when Intel gave up Trails and Wells for Lakes as the project names for the 64-bit computing devices. Up to that point, Intel embraced a package design philosophy they called “via-channel”. The pin-pitch was still fairly generous while rows of balls would be strategically depopulated so that there was just enough empty space for fan-out.
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Contract PCB Designer (part time) at Project X51
4 年Using uVias from L1 to L2 and then routing on L2 frees up L1 for GND plane, useful for shielding of RF noise (used this technique for over 20 years) - I have been doing 2+n+2 pcbs for over 15 years and 3+n+3 for over 10 years, just working on a 12 layer ridig-flex with cavity cutouts on various layers with HDI sequential build-up with uVias across all layers.