PCB Layout: A Reflection

I’ve been doing a lot of PCB layout for a client recently.

The EDA package I’m using is (perhaps) the market leader. It’s got a lot of functionality, most of which is either not truly necessary or is implemented in a rather over complicated way, given the main objective. I am familiar with the software having used it for a number of years, it's not my favorite.

A number of hardware engineers I know who use this software and who are responsible for layout dislike its many inexplicable quirks. Something that infuriates them, and me, more that the existence of the quirks (all EDA software has quirks) is that each new version comes with cool, new but, mostly unnecessary features. Problems and annoyances with the core functionality that are widely known are still not fixed. Why don’t the software companies concentrate on doing the fundamentals well?

I’m not going to claim that the days (which I do not remember) of drawing freehand or with a French curve on acetate with an alcohol pen were better or that I liked sitting at a light box transferring land patterns with a scalpel (never done it). I did start using EDA tools fairly soon after PCs became powerful enough to be useful in this area though, and, in terms of EDA tools, it doesn’t feel like we’ve come that far in some respects given that some of the biggest packages on the market still annoy their users enough to provoke the bears at Bear Instruments into full winter grumpiness. Haven't been this grumpy in winter since that bloody hare from the John Lewis advert woke me up a few years back.

The particular piece of software that’s attracted the grumpy snout of this bear has a new (in version 20 - a hint for the initiated) multi-board assembly view which crashes like it’s Windows 95/98 (sorry Bill but it spawned an acronym) – not good when you’ve got customer deadlines to meet.

I started thinking about how I started in layout and how small the software was (it fitted on a 3.5” floppy disk 1.44 MBytes and ran on MS DOS) and it didn’t crash, ever. It did, now and then, suffer from file corruptions but, so did a lot of software from that period. We kept backups – more or less as we do now, except on a floppy disk or a tape not in a version control or cloud system. Floppy disks were notoriously easy to corrupt so you’d keep a couple of backups in different locations.

The principle requirements of the software have not changed: to perform schematic capture, netlist driven layout at least 6 layers (the one I started on could manage 12), BOM generation and Gerber generation. Also to perform footprint (land pattern) generation and to allow the maintenance of a library for schematic components and land patterns. To save the data and allow it to be reloaded. Can’t really do without DRC either, which it had – not extensive but enough: pad – pad, pad – trace, trace – trace.

I dug up the software (from Dropbox where it lives for posterity (because I have trouble "letting go", apparently)) and fired it up with a little help from a DOS emulator and loaded up a circuit that I laid out in the mid-1990s. It was not my finest work. Single layer, no schematic and manually net listed (i.e. no schematic in EDA, a dangerous approach indeed!). After a bit of thought I remembered it. The IC is a PIC 16F84A and this board was the main board in a simple astronomical telescope positioning system. The PIC kept track of the telescope’s position based on some rotary encoders on the axes and displayed the right ascension and declination on a 2 line 16 character LCD. The alignment system (for the benefit of the amateur astronomers) was single star and your latitude (so more or less useless) and there was no way to improve the alignment by adding additional fixes. The code was all written in assembler. I could have done the net-listing with the software too, don't know why I didn't. The only thing missing from Ares 2.54 by modern standards is the ease of pulling component data from the internet automatically and the benefits of collaborative working (multiple users on the same project at the same time). I think the computer was a 386 with 4 MBytes of RAM, and that needed both slots. 40 MByte HDD.

About 25 years on, in a DOS emulator, the layout loads and the EDA software, despite being utterly primitive did everything I needed it to then and it would now too. If I tried to release the files to a customer, they wouldn’t be able to load them though.

Wouldn’t it be cool if I could load this layout in the modern version of this software, now called Proteus by Labcenter Electronics. Proteus is my favourite EDA software by the way, has been for many years. I know almost all it's quirks and they don't bother me. Sure it has weaknesses but I'm not going to ruin this rose tinted moment by listing them now. It's not a very long list anyway. I live, in hope, as much as in anticipation, of the day a client phones me up at Bear Instruments and says “We need some layout doing, no bandwidth in-house, do you use Proteus?” Hasn’t happened yet :’(

Surely a recent version of Proteus won’t open a file whose ‘modified’ date could still trigger the Y2K bug? I tried to import the layout and, without even the threat of an hour-glass, never mind a crash,

It says “Convert Ares 2.54 to version 8.07? (Y/N)”. OK, that is cute, it knows about really old versions but, it won’t actually be able to do it…

well, more or less. The crystal and the PIC have their top silk rotated and the PIC and poly-prop cap have their pads rotated which is weird but totally fixable. That is impressive, and it didn’t crash. Admittedly not the most useful feature unless you’ve got some very old IP to exploit but, it does demonstrate that the software engineering has stood the test of time. Can’t say that about all the current high market share EDA packages.

My layouts have moved on a bit since the early days and, just like the software, they’ve got bigger too. This one is part of a battery testing system I developed in 2012/13 when I was a postdoctoral research associate working in battery lifetime evaluation in automotive applications. I chose this one because no-one will wave a contract in my face due to me putting up a picture.

Not the most manufacturing friendly setup but, we only needed ten off and thick film resistors in ISOTOP packages were on back order of about 50 weeks presumably because of the Tsunami that hit Japan in 2011, hence the wire wound resistors, the copper rod and aluminium dropdowns to the FETs - did nothing good for the gate series inductance. If the resistors were ISOTOP too, like the FETs, it would have been slick. 60V max, 50 A / board, 10 boards per system all controlled by a master (not shown) which chatted to some National Instruments gear (I did the software for that too).

If you've made it this far, there's only one thing left: [email protected].