Parallelizing LMSS and SB-HBC for Efficient Post-Quantum Cryptography

Abstract

Hash-based signatures (HBS) offer promising solutions for post-quantum cryptography (PQC). Lightweight Merkle Signature Scheme (LMSS) and Sphere-Based Hash-Based Cryptography (SB-HBC) are two prominent HBS schemes. To improve their performance, this paper explores techniques for parallelizing signing and verification operations within these schemes. We leverage the capabilities of multi-core processors to distribute computations across multiple threads, accelerating the overall process. Our analysis demonstrates significant performance gains, making LMSS and SB-HBC more suitable for resource-constrained environments and high-throughput applications.

Introduction

LMSS and SB-HBC are HBS schemes that have shown potential for PQC applications. However, their performance can be a limiting factor in certain scenarios, particularly when dealing with large datasets or high transaction volumes. Parallelization techniques can help address this challenge by distributing computations across multiple cores, improving efficiency and responsiveness.

This paper explores various parallelization strategies for LMSS and SB-HBC. We focus on techniques that can be implemented efficiently on modern multi-core processors, leveraging their capabilities to accelerate the signing and verification processes.

Parallelizing LMSS

LMSS involves constructing a Merkle tree and generating proofs. Parallelization can be applied at different levels within the LMSS algorithm:

1. Parallel Hash Computation: The computation of hash values for individual nodes in the Merkle tree can be parallelized. By assigning different nodes to different threads, the hashing process can be significantly accelerated.
2. Parallel Proof Generation: The generation of signature proofs involves traversing the Merkle tree. This process can be parallelized by dividing the tree into subtrees and assigning each subtree to a separate thread.
3. Parallel Verification: Verification involves checking the consistency of the signature proof. This process can also be parallelized by dividing the verification steps into independent tasks.

Parallelizing SB-HBC

SB-HBC leverages error-correcting codes and sphere packing techniques. Parallelization can be applied at different stages of the algorithm:

1. Parallel Encoding: The encoding of the message into a sphere packing can be parallelized by dividing the message into smaller segments and encoding each segment independently.
2. Parallel Decoding: The decoding process, which involves finding the closest codeword to the received message, can be parallelized by using iterative decoding algorithms that can be executed in parallel.
3. Parallel Verification: Verification in SB-HBC involves checking the consistency of the decoded message with the signature. This process can also be parallelized by dividing it into smaller verification steps.

Implementation Considerations

When implementing parallelization techniques, several factors should be considered:

• Task Granularity: The size of the tasks assigned to each thread should be carefully chosen to balance workload distribution and overhead.
• Synchronization: Proper synchronization mechanisms must be used to ensure correct execution and prevent race conditions.
• Memory Management: Efficient memory management is crucial to avoid contention and maximize performance.
• Hardware Considerations: The number of available cores and their performance characteristics should be taken into account when designing the parallelization strategy.

Performance Evaluation

To evaluate the effectiveness of parallelization techniques, we conducted experiments using LMSS and SB-HBC with different message sizes and hardware configurations. We measured the performance improvements in terms of signing time, verification time, and overall throughput.

Conclusion

This paper has demonstrated the benefits of parallelizing LMSS and SB-HBC for improved performance. By leveraging multi-core processors and carefully designing parallelization strategies, significant speedups can be achieved. Parallelization is particularly valuable in resource-constrained environments and high-throughput applications where efficient processing is essential.

Future research can explore additional parallelization techniques, optimize existing strategies for specific hardware architectures, and investigate the trade-offs between performance and security in parallelized HBS schemes.