PAPER: Solving Complex Users assertions
https://SystemVerilog.us/fv/SolvingComplexUsersAssertions.pdf
The verificationacademy.com/forums/ is an interesting interactive SystemVerilog forum where users seek solutions to real application issues/problems. Many of those questions are about assertions, and SVA has very specific set of rules that do not necessarily address complex users' requirements. This paper brings a collection of a few most interesting and challenging users' questions and provide solutions along with explanations about getting around (or working with) SVA, or using other alternatives (see SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue). It turns out that many of these solutions require a different point of view in approaching the assertions, and often require supporting logic. All code along with simple testbenches is provided.
Design Verification Engineer
6 年Thanks for sharing, this is useful! I have a concern about 1.6 though: 1.6 Sig "a" shall change values "n" times between sig "b" and sig "c" the given solution for any N can fail for non-consecutive changes on signal b because count is incremented every time sig a is not changed in t_abc_dyn() task. So when sig c is asserted, the count value can be greater then N and it will print a fake error. For example for N=10, the given solution can produce different results than the following: ap_abc: assert property( $rose(b) |-> $changed(a)[=10] intersect c [->1]);