Overcoming Verification Challenges in 3DIC Design
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Welcome back to Design with Calibre’s LinkedIn Newsletter! In this month's issue, we’ve invited John Ferguson , Senior Director of Product Management, Calibre 3DIC to discuss the developing world of 3DIC!
It’s no secret… 3D integrated circuits (3DICs) are emerging as a revolutionary approach to design, manufacturing and packaging in the semiconductor industry. Offering significant advantages in size, performance, power efficiency and cost, 3DICs are poised to transform the landscape of electronic devices. However, with these advancements come new verification challenges that must be addressed to ensure successful implementation – which is why I’m excited to have the opportunity to explore with all of you the unique aspects of 3DIC design and the innovative solutions available to tackle these verification challenges!
Understanding the basics
Design teams have long recognized that mechanical stresses and temperature changes can affect electrical behavior. In traditional integrated circuit (IC) or system-on-chip (SoC) designs, these impacts are largely managed because all devices are on a common silicon die. Designers use specific rules to separate devices from local impacts, ensuring that most issues are minimized or avoided. By extracting additional device parameters, gross deficiencies can be flagged for review, allowing any further concerns to be captured during post-layout simulation. However, in the realm of 3DIC design, those safeguards are no longer practical.
Traditional IC and SoC designs vs. 3DIC challenges
Unlike traditional ICs, 2.5D and 3DICs are composed of multiple individual chiplets, each tailored to a specific process node best suited for their particular purpose.
Diverse connection methods in 3DICs
3DICs can connect chiplets in various ways:
These methods can be combined within a single 3DIC assembly, integrating components of different materials in all three dimensions. This introduces new stresses and affects access to thermal heat sinks. Manufacturing processes, power and active device toggling also introduce new thermal impacts, creating several new verification challenges for 3DIC designs.
Addressing verification challenges in 3DIC designs
The primary challenge is ensuring that active chiplets in a 3DIC assembly behave electrically as intended. Calibre Design Solutions addresses this by extending the Calibre infrastructure with the Calibre? 3DSTACK tool to define the 3D stack-up. This stack-up definition can be created using rule deck syntax, automated with Siemens Xpedition? Substrate Integrator (XSI) platform or translated from the 3Dblox? open format. This insight allows the Calibre engine to understand the connectivity and geometric interfaces across all components in the assembly, enabling a single deck and run to identify design rule checking (DRC) or layout vs. schematic (LVS) issues, and generate a post-assembly netlist for further analysis. This definition also drives automation of cross-die parasitic coupling impacts, laying the groundwork for 3D-level analysis of thermal and stress impacts.
Power network and thermal analysis in 3DICs
The first step is creating the initial power network. The Siemens mPower? solution can use the output of the 3DSTACK run to extract connectivity and any coupling across the chiplets. Adding the individual chiplet networks and internal connectivity to this data allows for the creation of power maps to drive thermal analysis.
Using innovative Calibre technology, 3DIC thermal analysis leverages the same assembly definition created for 3DSTACK connectivity extraction. Appropriate material property definitions for each component and boundary conditions are captured in chiplet specific thermal models which are automatically passed to an integrated, customized ?Simcenter? Flotherm? thermal solver to generate thermal maps under the hood. The Calibre software’s detailed layer information for individual chiplets allows it to generate accurate individual die thermal models. By leveraging chiplet-specific layout and connectivity, thermal impacts can be transformed to the device level, enabling accurate post-assembly simulations or electromigration and voltage (EMIR) analysis.
Capturing electrical impacts of mechanical stresses
3DIC designers also need to capture electrical impacts of all stresses on active chiplets. Using the same assembly stack-up definition and mechanical stress properties for each material, the stress information would be pushed down to the device level for accurate post-assembly simulation and analysis at the active chiplet levels.
Interplay between mechanical stress, thermal impacts and electrical behavior
Mechanical stresses induce heat. Thermal impacts induce mechanical stress. Both affect electrical behavior, which can generate more heat. Mitigating these impacts involves:
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Automating cross-simulation for 3DIC design teams is possible, but early design analysis and floorplan selection are crucial to avoid late-stage issues.
Early design analysis and 3DIC floorplan selection
To identify and address issues earlier in the design flow, tools like XSI can specify several 3D floorplan options. While not all details for all layers and materials will be available, this approach enables sufficient early analysis to rule out configurations with serious flaws. As design components mature, further iterations become more accurate, simplifying and speeding the analysis required when chiplets are placed in context.
Proven solutions for ensuring successful 3DIC designs
3DIC design offers significant promise in size, performance, power, and costs but introduces new verification challenges. The industry continues to address these challenges, ensuring 3DIC designs meet manufacturability requirements and implement intended electrical behavior properly.
By leveraging proven and emerging tools and early design analysis, 3DIC designers can navigate these challenges effectively, paving the way for successful 3DIC implementations.
There’s still so much more to talk about in the realm of 3D integrated circuits, but I’ll sign off for today. Thanks for reading and let’s talk about 3DIC again soon!
Senior Director of Product Management, Calibre 3DIC
You can find a variety of more resources from us on John’s talking points here:
Technical Paper: Successful 3DIC design, verification, and analysis
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