OSVVM On The Road

Back from teaching our OSVVM bootcamp in Sweden and FPGA Kongress in Munich Germany.  It has been a great couple of weeks.  I even snuck a little vacation in there.

It all started in Gothenberg, Sweden with our Advanced VHDL Testbenches and Verification class - OSVVM bootcamp.  At this class another group of students learned the OSVVM approach to Transaction-Based Models and Testbenches, error handling and message filtering (Alerts, Logs, and Affirmations), scoreboards, synchronization utilities (WaitForBarrier, ...), randomization, functional coverage, and memory modeling.  

Two weeks later at FPGA Kongress, I presented three 45 minute sessions on OSVVM and a 90 minute hands on tutorial.  The paper sessions covered an OSVVM overview, our OSVVM AXI Lite Master Model (see OSVVM/VerificationIP on GitHub), and the OSVVM way of writing transaction based test cases.  

Our tutorial had 40 attendees - it is great to see that level of interest. In the tutorial, attendees wrote an AxiStream model and test cases from scratch.  The result was impressive - most attendees were able to write the model and the first test case within 50 to 90 minutes.   The tutorial also gave attendees the opportunity to use scoreboards, randomization and coverage modeling in their OSVVM testbench.

Finally one thing I am often asked, why is the OSVVM Bootcamp 5 days?  The answer is simple, no one would attend a 7 day class.   

If you are at DAC next week, I will be presenting VHDL-2018 and OSVVM in the Aldec booth.  Be sure to look me up.