OSVVM: Call for Participation

In the fall of 2019 Open Source VHDL Verification Methodology (OSVVM) was accepted into the pilot program for IEEE Open Source.  Recently we received the go ahead to upload our repositories onto the IEEE Open Source GitLab hosting platform.  You can find us at: https://opensource.ieee.org/osvvm

We would like the invite the VHDL verification community to join us in developing OSVVM.  To be able to make contributions we will need you to fill out the IEEE contributor license agreement (CLA).  Download a form using the link below and email to the address in the form: https://opensource.ieee.org/community/cla/apache

I realize you may hate forms.  I do too.  However, these forms help protect a project against risks related to copyright and patent infringements.  IEEE pays close attention to these items as organizations have tried all kinds of capers in the standards community. 

About OSVVM

Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries one can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC.

According to the 2018 Wilson Verification Survey, OSVVM is the

• #1 VHDL Verification Library
•  #1 FPGA Verification Library in Europe (ahead of SystemVerilog)

The OSVVM utility library offers the same capabilities as those provided by other verification languages (such as SystemVerilog and UVM):

• Transaction-Level Modeling
• Constrained Random test generation
• Functional Coverage with hooks for UCIS coverage database integration
• Intelligent Coverage Random test generation
• Utilities for testbench process synchronization generation
• Utilities for clock and reset generation
• Transcript files
• Error logging and reporting - Alerts and Affirmations
• Message filtering - Logs
• Scoreboards and FIFOs (data structures for verification)
• Memory models

The OSVVM verification component library provides the following models. The verification components all use records for the transaction interfaces, so connecting them in a testbench only requires a single signal.

• AXI4 Lite Master
• AXI4 Lite Transaction Slave model
• AXI4 Full Master (coming soon)
• AXI4 Full Memory Slave model (coming soon)
• AXI Stream Transmitter
• AXI Stream Receiver
• UART Transmitter (with error injection)
• UART Receiver (with error injection)

Testbenches for each model are in the Git repository, so you can run a simulation and see a live example of how to use the models.