OS Fundamentals – Part 2: Virtual Memory and Paging: Expanding Memory Beyond Installed RAM

Understanding virtual memory is key to grasping how modern operating systems and CPUs manage memory. When the CPU's MMU (Memory Management Unit) is enabled, it generates virtual addresses, which are mapped to physical addresses in RAM through translation tables cached in TLBs (Translation Lookaside Buffers). For example, a 48-bit address spans 256 TB of addressable space, while a 64-bit address can span 16 EB (exabytes). However, most computers don’t have enough RAM to fill their entire addressable space. This is where virtual memory (VM) and paging come to the rescue.

With paging, the OS uses the MMU and TLBs to allow the CPU to generate a full range of addresses, even if the physical RAM is much smaller. Let’s look at a 1 GB address space with a 4 KB page size. The OS breaks down this address space into pages (each 4 KB), and only loads the necessary pages into RAM as needed. When a program accesses an address not currently loaded in RAM, a page fault occurs. The OS unloads an existing page and loads the required one, ensuring that virtual addresses are mapped correctly to physical addresses without needing the program to be recompiled for different memory configurations.

Virtual Address to Physical Address Mapping: Understanding Page Tables

When the CPU accesses memory, the virtual address is divided into two parts:

1.???? Page number: Used to look up the physical page in the page table.

2.???? Offset: The lower bits that remain the same in both virtual and physical addresses, allowing fast access within a page.

Virtual Address = Page Number + Offset

Physical Address = Frame Number + Offset

The page table maps the virtual page number to a physical frame number. The offset remains the same, which allows efficient memory access since only the base address (page/frame number) is translated.

In the above example, different virtual pages map to different physical frames, but the offset within each page remains the same.

Page Table Entry (PTE): Bits Breakdown

Each entry in the page table contains metadata and flags that manage how the memory is accessed. Here’s a breakdown of a typical page table entry (PTE):

1.???? Base Address: Points to the physical memory location of the page.

2.???? Offset: Remains the same between virtual and physical addresses for quick translation.

3.???? Access Control Flags: Control permissions such as read/write/execute.

4.???? User/Supervisor: User privilege access or Kernel privilege only access

5.???? Cache Control Bits: Cache is enabled or not for the specific page

6.???? Present Bit: Indicates if the page is currently in memory (used for handling page faults).

Memory Protection and Access Control

Virtual memory not only extends the addressable space but also enforces memory protection. The access flags in the page table entry specify whether a page is readable, writable, or executable. Additionally, CPUs operate at different privilege levels (like user mode and kernel mode), and these bits ensure that unauthorized accesses (like user programs trying to execute privileged instructions) are blocked.

The offset bits, though unchanged in translation, can be used for memory protection. For example, if the virtual address has an illegal combination of access flags (e.g., trying to write to a read-only page), the system triggers a protection fault.

Memory Space Isolation in Process Management

An interesting application of virtual memory is in process memory isolation. In a typical 32-bit virtual address space (such as in Linux), all processes have access to a 4 GB address range. Usually, 0 to 3 GB is allocated for user space, and 3 to 4 GB is reserved for the kernel space. Interestingly, all processes see the same virtual address range—so how does the operating system prevent conflicts between processes trying to access the same virtual memory addresses?

The OS uses virtual memory to isolate memory spaces for different processes. Each process has its own translation table (TTL), mapping virtual addresses to different physical addresses. For example:

• Process 1 might have virtual address 0x1000 mapped to physical address 0x8000.
• Process 2 might have virtual address 0x1000 mapped to physical address 0xA000.
• Process 3 might have virtual address 0x1000 mapped to physical address 0xC000.

When switching between processes, the OS’s process management component swaps the translation tables for each process. This ensures that the same virtual addresses in different processes map to different physical locations, preventing conflicts. If a required page isn't present in RAM, a page fault is triggered, and the OS loads the necessary page into memory, repeating the process as needed.

Virtual memory and paging are fundamental to modern operating systems, enabling efficient memory management, security, and flexibility. Through page table entries, operating systems manage access control, expand memory beyond physical limits, and ensure smooth operation of complex applications, regardless of the installed RAM.

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