Online histogram design

Leaks from the Interrogation room?

After start signal n clocks and n data words of w-bits are transmitted.

Design a system that calculates occurrences’ number of each data value (histogram).

Solution 1:

Create array of 2^w rows of counters of w-bits wide.

Entry data points the counter to be incremented by one.

In the end of the session each counter contains the number of its own index occurrences.

This is a brief description. Some details and timing are left to the reader.

Further explanations can be provided by contacting the writer. Contact details are at the end of the article.

The advantages of the design are its simplicity and its adaption to a CPLD without a RAM.

Its disadvantage is its cost comparing a design using internal RAM in FPGA.

The interested one for a solution with RAM or implementation in HDL can contact with me.

Complete and detailed solutions can be ordered for questions in the above subjects, including an explanation in a direct call 972-52-5597916, which will be given at the client's free time after examining the detailed solution.

Mob: 972-52-5597916

ramiattas@gmail.com

https://sites.google.com/site/programrole

Rami Attas electronics consultant?(FPGA CPLD)??????????

Technion Institute Electrical Engineering Faculty;

Professional experience:

Long experience in designing electronic systems composed microprocessors digital logic devices (FPGA) and in hardware and software (C) integration.

ramiattas@gmail.com 972-52-5597916

https://sites.google.com/site/programgate