Non-Monotonic Signals in Circuits

Often times, I have to debug interconnect models, SPICE or Spectre netlists, SPEF, Extended SPEF files, DSPF files, and LEF/DEF files.

My go-to solution is to use Boost Graph Library to build the graphs from adjacency matrices of these electrical circuits and then use C++/Qt to display all paths connected, shortest paths, user selected paths, and search paths that are unreachable. While often basic, these circuit graphs help me to understand the electrical properties such as Static Timing Analysis, Stage by stage delay calculation, Timing debugs, and Signal Integrity. Debugging abnormal behavior using circuit graphs is easier than debugging through numerous specific paths of the design in text report form. Isolating that one off mystery signal behavior at a specific part of the circuit is one of the time consuming parts of circuit debugging. Here is one such case that is not immediately obvious-- a non-monotonic current or voltage waveform (see Fig 1.) can introduce erroneous behavior in subsequent stages of your circuit. Using graph theory techniques previously discussed and waveform processing (or modeling) at each stage can help in catching the precise stage where non-monotonic behavior exists.

While C++/BGL and Qt work beautifully in visualizing the electrical behavior and physical connectivity of a design, lately, I am realizing that there are easier ways to debug such problems using graph theory, Spectre simulator, and a little math (first order differential equations. See Fig 2. If you simulate this circuit by injecting non-monotonic waveforms you will appreciate why fixing non-monotonic waveforms in circuit analysis is absolutely important).

First, let us look at a current waveform that we may have computed at a specific stage in timing analysis. If that current waveform has non-monotonic behavior, that can lead to poor results since measurements can be off due to the inflections (non-monotonicity). Such currents?or electrical signals can distort the reality if we use them in our circuits resulting in abnormal behavior. Therefore, such non-monotonic delay or current waveforms require a careful analysis to understand precisely how and why any inflections are manifested at all on that waveform and resolve the problem by replacing the bad cell instance. Often, this bad cell is likely a result of poor cell characterization. So, re-characterizing such cells is the practical choice.

In the process of resolving such problems, I ended up building a whole netlist parser to visualize graphs and inject specific waveforms on signals in these graphs to study their electrical behavior for various waveform shapes. This has undoubtedly helped me debug multiple delay cal, STA, Power, EM/IR problems much quickly.

Reach out if you want to discuss more on how such small solutions can be highly impactful as we develop high density advanced node chip designs.