The Next Generation of Transistor Candidates, Not Silicon!

Semiconducting carbon nanotubes are robust molecules with nanoscale diameters that can be used in field-effect transistors, from larger thin-film implementations to devices that work in conjunction with silicon electronics, and may be used as high-performance digital electronics as well as radio frequency and sensing The platform of the application. The latest progress in materials, devices and technologies of carbon nanotube transistors is briefly reviewed. The most broadly impactful advances from the development of single-nanotube devices to aligned nanotubes and even nanotube films are highlighted. There are still hurdles to be addressed, including material synthesis and process control, device structure design and transport considerations, and further demonstration of integration, improving reproducibility and reliability; however, more than 10,000 devices on a single functional chip have been achieved so far integrated.

A transistor is an electronic switching device that is capable of digital computation based on its on (binary 1) and off (binary 0) operations. In the early days of integrated circuits, it was clear that reducing the size of transistors would drive better chip-level performance, which is now known as Moore's Law. The single most important dimension of this scaling is the semiconductor channel length, which is the distance over which current flows, or the distance to turn the device on and off as controlled by the gate electric field. Although initial channel lengths were many microns in size, proposals to extend semiconductor channels to the molecular size limit (a fraction of a nanometer) date back to the mid-1970s. Decades of research into electron transfer through conjugated organic molecules (thought to replace silicon channels) have highlighted several important challenges for such molecular transistors. The most important issues include low stability and difficulties in efficient gating and forming reliable electrical contacts with molecules.

To match or exceed the performance of silicon electronics, it is clear that new channel materials must have similar stability. Among molecular options, semiconducting single-walled carbon nanotubes (CNTs) have several advantages. Nested multi-walled carbon nanotubes are effective metals at room temperature and thus have limited usefulness as transistor channels. In this review, CNT will mean single-walled carbon nanotubes. Semiconducting carbon nanotubes consist of cylindrical shells of hexagonally arranged carbon about 1 nanometer in diameter. The electrons only move forward or backward, and the wave function wraps around the nanotube, forming a one-dimensional (1D) semiconductor with an energy band of a few hundred millielectronvolts. These materials are stable in air and can be manipulated by various processing methods commonly used in the semiconductor industry. Early demonstrations of field-effect transistors (FETs) by covering semiconducting carbon nanotubes on metal electrodes led to continued research activity with the goal of fabricating reproducible, scalable and High-performance devices integrated into dense circuits.

The widespread interest in carbon nanotube semiconductors has also inspired intense and ongoing exploration of other nanomaterials, including semiconducting nanowires, 2D graphene, transition metal dichalcogenides, and xenon. Although the choice of nanomaterials is growing, carbon nanotubes stand out in terms of stability, band gap, and excellent electrical and thermal properties unmatched by other candidate materials. Here, we review recent material, device, and technological advances in carbon nanotube transistors, establishing the substantial promise and remaining challenges of this molecular transistor. Advances in this field will relate to the most important potential applications of carbon nanotube transistors, as shown in Figure 1. Two of the most prominent potential applications are high-performance (HP) computing chips and thin-film transistors (TFTs) for display backplanes and the Internet of Things (IoT); Table 1 summarizes some target performance metrics for these applications.

Figure 1: Wide range of potential applications for carbon nanotube transistors. Device performance versus cost and complexity for some of the most important potential applications of carbon nanotube transistors is illustrated. Applications range from tiny thin-film devices (e.g. printed electronics, biosensors) to 3D integrated BEOL devices (e.g. heterogeneous 3D layers integrated onto silicon CMOS) and scale high performance (HP) FETs [e.g. low voltage very large scale integration (VLSI)] , whose performance increases correspond to increases in integration cost and complexity. Lch, channel length.

Table 1: Several target metrics for two prominent CNT transistor applications. Values are approximate based on achieving best performance. It is worth noting that while some of these goals have been achieved, one of the most important challenges has been achieving them simultaneously (e.g., high conduction current with low subthreshold swing, which is a measure of how much gate voltage is required to modulate the current). High-performance FETs are used in applications such as central processing units (CPUs) in servers, and TFTs are thin-film transistors used in display backplane electronics.

Harnessing the advantages of carbon nanotube semiconductors requires overcoming several material science hurdles. Just as silicon must be purified and doped to be a useful channel material, synthesized carbon nanotubes can be both metallic and semiconducting, and must be purified to semiconductors only for use in transistors. Whether carbon nanotubes are metallic or semiconducting depends on how the hexagonal lattice is wrapped into the tube. The structure is most easily observed by rolling rectangular sections of atomically thin graphene's sp2-bonded hexagonal carbon lattice into one-dimensional cylinders with a diameter of about 1 nanometer and a length of 102 to 108 nanometers. The vector that defines the rectangular cross-section relative to the width of the graphene lattice is often referred to as the chirality vector, and ultimately determines the diameter, helicity, and conductivity of the carbon nanotubes.

In addition to specifying the physical structure of carbon nanotubes, the chirality vector imposes explicit quantum-mechanical boundary conditions on the electronic band structure, which means that for random tube closures, about 33% of the carbon nanotube chirality is metallic, and about 67% are semiconductors. Furthermore, in semiconductor chirality, the band gap is approximately inversely proportional to the carbon nanotube diameter. Since CNT transistors require a semiconducting channel, ideally with a well-defined and consistent bandgap, the ability to scaleably synthesize and isolate CNTs with atomically precise chiral vector control is the ultimate goal for high-performance CNT integrated circuits. Target.

Controlled Synthesis of Carbon Nanotubes

Carbon nanotubes are synthesized by introducing carbon-containing raw materials and metal catalysts (usually iron or nickel) into a growth chamber where energy is added by heat, light, or plasma excitation. Since carbon nanotube growth typically occurs at temperatures where these catalysts undergo extensive recombination, it is difficult to control the chiral vector, and a range of carbon nanotube diameters and two electron types are produced; in order to control the chirality of carbon nanotubes, it has been A lot of effort was spent. These approaches include the use of refractory catalyst particles such as W-Co alloys of well-defined size and shape, which retain their structure at the growth temperature and thus can drive predictable nucleation of targeted CNT chirality (Fig. 2A), Add molecular seeds with structures that closely match the chirality of the targeted CNTs, or in "CNT cloning" seed the CNTs themselves. While custom catalysts or seeds help control synthetic outcomes, many other growth parameters also play a role, including temperature, pressure, flow rate, and applied electric field—thus growth optimization requires searching a broad parameter space. To accelerate this quest, autonomous growth using closed-loop iterative experiments promises to rapidly determine synthesis conditions that minimize CNT structural polydispersity.

Semiconducting Carbon Nanotube Separation

Since optimized CNT growth procedures still lack sufficient monodispersity for wafer-scale transistor applications, post-synthesis separation methods are required to sort the grown CNTs by diameter, chirality, and electron type. Fortunately, CNTs are comparable in size and shape to biological macromolecules, allowing many CNT separation methods to improve upon already developed biochemical separation methods. In density gradient ultracentrifugation (DGU), carbon nanotubes are first dispersed and encapsulated by a mixture of surfactants that are effective for different carbon nanotube separation targets (including chiral vector, chirality, electron type and diameter) are selective and then separated by buoyant density in a water density gradient. Although DGU is sufficiently scalable to be commercially viable, other strategies in biochemistry have also been vigorously developed, including gel chromatography and dielectrophoresis. The latter approach has the added benefit of aligning assembled CNTs between pre-patterned electrodes.

Methods from polymer chemistry have also been used to isolate CNTs, including aqueous two-phase extraction and identification of the polymer-selective dispersion-targeted CNT chirality using the structure of the encapsulated nanotubes (Fig. 2B). In all cases, the purity of semiconducting CNTs has reached the limit of detectability (~99.9%) for optical spectroscopic characterization and begins to provide sufficient monodispersity for many CNT transistor applications. The ultimate goal for high-performance digital transistors is to achieve 99.9999% pure semiconducting carbon nanotubes (see Table 1)—the higher the purity, the better the corresponding performance. In addition, any molecular wrappers (such as surfactants or polymers) should ideally be completely removed after CNT deposition, as this would create unwanted residues that would interfere with electrical contacts, gates, and gates in CNT transistors. control efficiency and transmission.

Other Material Considerations

Transistors also require electrical contacts, doping and dielectrics. Since contacts from commonly used metals (e.g., Au, Pd) tend to generate Fermi level alignment near the CNT valence band, p-type behavior from hole implantation is easily achieved in CNT transistors. However, the complementary requirement of p-type and n-type transistors in digital circuits means that controlled n-type implantation and/or doping is required.

Electron-donating adsorbents, such as organo-rhodium compounds, combined with ALD-encapsulated layers can fabricate highly stable n-type CNT transistors (Fig. 2C). Charge-selective contacts based on metal work functions, such as p-type implanted Pd and n-type implanted Sc, also enable complementary CNT transistors. In addition to metal selection, interfacial material considerations and overall contact structures also play a role (see Figure 2D for an example of an end-bonded contact structure using Mo). The extended region of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), between the source or drain and the gate-controlled semiconductor channel, requires stable doping with a well-controlled doping level, which is the difference between the series resistance and the parasitic capacitance. Optimizing the trade-offs between them—a feat that has yet to be reliably accomplished in carbon nanotube transistors. For the gate dielectric layer, specific materials such as Y2O3 exhibit near-ideal performance with high dielectric constant κ and conformal dielectric coatings on CNTs after oxidation of deposited yttrium. A more conventional approach, using atomic layer deposition of Al3O3 and HfO2 bilayer dielectrics, enables transistors with gate lengths of 10 nanometers and gate leakage currents comparable to state-of-the-art Si transistors. After integrating all these optimized materials, carbon nanotube transistors have been demonstrated to exceed the performance of existing silicon integrated circuit technology, which will be discussed in subsequent sections.

Figure 2.: Examples of materials for high-performance CNT transistors include synthesized CNTs, purified CNT mixtures, doping strategies, and contact metals.

(A) Templated carbon nanotube growth of targeted chirality using refractory W-Co nanocrystalline catalyst. CVD, chemical vapor deposition; SWNT, single-walled nanotubes.

(B) Selective polymer dispersion enables scalable separation of targeted CNT chiralities from growing polydisperse mixtures, as demonstrated by absorption spectroscopy, shown on the left; synthesis of sorted CNTs is shown on the right. bottle photo. E11 and E22 are absorption peaks; SFM, shear mixing.

(C) Electron-donating organo-rhodium compounds encapsulated with ALD alumina for stable n-type CNT transistors. Black is the CNT layer, orange is the dopant layer, and red is the seed layer for dielectric growth.

(D) When reacting to form terminal carbides, the contact length (Lc) of molybdenum to carbon nanotube transistors can be scaled down to sub-10 nm dimensions while maintaining efficient charge injection.

Carbon Nanotube Transistor Design

The initial focus of CNT transistor research was the use of individual CNTs as channels (see Figure 3, a and b) and the demonstration of ballistic transmission and digital circuit operability. While devices with individual nanotube channels are still of interest for sensing applications, they are no longer considered suitable for digital or radio frequency (RF) electronics based on the need for higher current flow than can be provided by individual nanotubes. Although the current-carrying capacity of carbon nanotubes is amazing [~109 A cm?2], they are only about 1 nm in diameter and only generate about 10 mA of current per carbon nanotube. Therefore, recent work has mainly focused on having multiple CNTs in channels.

Aligned Arrays of Carbon Nanotubes

Ideally, the carbon nanotubes in the transistor channel would be perfectly arranged in a parallel array with a controlled pitch of 2-5nm, similar to how silicon fins are arranged in modern transistor technology (finfet). Realizing such arrays remains a challenge. If the carbon nanotubes are too tightly packed (or bundled), crosstalk (electric field shielding) and effective gating problems arise. If the carbon nanotubes are too far apart, the current density (current per transistor width) will be insufficient. For digital systems with high densities of carbon nanotube transistors, variations in the spacing between carbon nanotubes can also detrimentally affect overall power, latency, and noise margin.

Recent progress has been encouraging, including small-scale demonstrations using DNA-directed assembly to control carbon nanotube spacing to 10 nm. There are also wafer-scale high-throughput strategies using various forms of solution-phase assembly (also known as size-limited self-alignment or liquid crystal interface assembly), achieving a pitch of 20 nm in one report (Fig. 3, C and D), A pitch of 5 to 10 nm was achieved in another report. The main difference between the two studies is the polymer used to encapsulate the CNTs and the solid-phase technique used to deposit the CNTs onto the substrate array. Still, these methods require further work to remove unwanted residues from the processing of the solve stage and to achieve a more consistent and controlled alignment (without bundling) in all directions at even spacing.

Carbon Nanotube Film

Due to the difficulty in achieving aligned arrays with controllable spacing, some researchers have used unaligned CNT networks or thin films (Fig. 3, E to H). Although these misaligned films are not conducive to carrier transport, contacting and gating nanotubes, misaligned carbon nanotube networks achieve high performance in nanoscale transistors.

Furthermore, carbon nanotube films can be deposited by using printing techniques, including roll-to-roll and direct-write methods (Fig. 3H), which makes them attractive for TFTs. These larger TFTs (on the order of tens of microns) have a different application space than high-performance nanoFETs, including sensors, flexible electronics, IoT, and display backplanes. For TFT applications, CNT films compete well with existing semiconductor options such as organics and polymers, metal oxides, and low-temperature polysilicon (LTPS).

When carbon nanotube films were used in FETs with nanoscale channel lengths (<100 nm), most nanotubes bridged the entire channel, even if they were not perfectly aligned (Fig. 3F). In the microscale lengths of TFTs, the nanotubes in the thin-film channels are not large enough to traverse the channel, but instead operate as a permeable network in which electrons travel from CNT to CNT during source-to-drain transport (Fig. 3G ). Compared with long-studied organic semiconductor TFTs, CNT-TFTs have higher mobility (10–100 cm2V?1s?1) and stability under bias voltage, in air, or both.

Advanced Gating Structure

In addition to the density and arrangement of nanotubes in the channel, the gate structure of carbon nanotube transistors has advanced in many aspects. For nanoscale FETs, the main goal is to maximize gate control of the CNT energy band in the channel, which is achieved by strong gate coupling, usually expressed as a small scale length λ. The scale length depends on the gate geometry as well as the thickness and permittivity of the gate dielectric and semiconductor channel. A generally accepted approximation is that channel lengths greater than 3λ will ensure that deleterious short channel effects are avoided.

Due to their inherent small size, CNTs offer advantages for massively scalable devices. Although it is ideal for FETs to have a gate-full geometry to minimize λ, and demonstrations of carbon nanotube gate structures have been reported, studies have shown that neither the bottom gate nor the top gate In both geometries, channel lengths much smaller than 10 nm (as short as 5 nm) can be obtained. Although the geometry of the gate is different for TFTs, it is not critical and is mainly limited by the gate dielectric material and application requirements.

Source-Drain Contact Structure

For high-ratio carbon nanotube transistors with small footprints, not only does the channel length need to be on the nanometer scale, but the source and drain contacts also need to have minimal dimensions while still providing efficient ohmic charge injection. Palladium contacts reach the quantum limit of 6.5 khm per CNT at 10nm contact length, and in p-side contacts the metal sits on top of the CNT without any chemical bonding, although this needs to be done in higher yield and reproducible to fulfill. Alternatively, an edge-contact structure would provide ideal scalability and has been demonstrated by reacting with carbon nanotubes to generate carbide end-bond contacts with contact lengths below 10 nm (Fig. 2D). Regardless of their geometry, contact with carbon nanotubes is the main factor determining the overall performance, and the combination of materials, structure, and processing must be further improved to produce p-type and n-type carrier injection with high consistency and low resistance. touch.

Technology Demonstration

High-performance, power-efficient digital logic

Although many applications can benefit from the properties of carbon nanotubes, digital logic applications have received the greatest attention (Figure 4) because of their potential to outperform existing Si technologies in terms of performance and energy efficiency. Such typical high-performance devices come from aligned arrays of carbon nanotubes that can achieve high on-state currents at relatively low voltages (Fig. 4, A to C). As shown in Figure 4D, at the 2nm technology node (EDP, or switching energy), doped extended and multilayer high-density CNT-gated all-round CNT transistors are expected to exhibit up to 7 times the Energy Delay Product (EDP) benefit, which is the product of the time of an on-off cycle and power consumption, and is a measure of energy efficiency). As mentioned earlier, due to their ultrathin structure (about 1 nm), CNT transistors offer excellent electrostatic control even over the gate length, limited only by direct source-drain tunneling. Parasitic capacitance is a key factor affecting speed and energy efficiency, accounting for 70% of the total capacitance of modern silicon transistors. Due to its ultra-thin structure, carbon nanotube transistors have very low parasitic gate-source or gate-drain capacitance. These two key properties of CNTs, along with high transfer and injection speeds, are the physical basis for high-performance, energy-efficient digital logic.

(A and B) Subthreshold (A) and output characteristics

(B) of a CNT transistor fabricated in an aligned array of approximately 150 CNTs per micrometer, which can achieve an on-state current of >1 mA μm?1. Ids, drain current; Vds, drain-source voltage; Vgs, gate-source voltage.

(C) Device schematics of a silicon nanosheet transistor and a carbon nanotube aligned array transistor with two stacked channels.

(D) Projected energy versus frequency Pareto curves of Si nanosheets and CNT transistors on the 2nm technology node of the inverter ring oscillator.

As mentioned earlier, many of the basic building blocks of CNT transistor technology have been demonstrated. At the circuit or system level, a fully functional static random access memory (SRAM) array, a monolithic 3D imager, and a 16-bit RISC-V (where RISC is reduced to an instruction set computer) processor >14,000 transistors ( Fig. 5B) Fabricated entirely from CNT transistors. Furthermore, wafer-scale fabrication of CNT transistors has been demonstrated in foundries using 200 mm wafer processing technology (Fig. 5A). Fabricating and designing carbon nanotube transistors using the same tools and infrastructure as commercial semiconductor technologies can help lower the barrier to mass production of carbon nanotube devices.

(A) 200 mm silicon wafer with carbon nanotube transistors processed in a commercial silicon foundry. The bottom left shows an image of a single die, or chip, in a wafer, and the bottom right shows a schematic of a carbon nanotube transistor structure. D, drain; G, gate; K, relative permittivity; S, source.

(B) Optical image of a RISC-V processor implemented with CMOS carbon nanotube transistors (RV16X-NANO), including showing CNT circuits (false colors indicate different metal layers) and individual CNT devices (CNT High magnification image of detail highlighted in yellow).

(C to E) Image and schematic of a 3D N3XT chip with integrated CNT transistors and RRAM memory layer on top of silicon logic (C); cross-sectional TEM image showing bottom Si logic layer, RRAM memory layer, and two CNT transistor layers [C Nanotube field-effect transistors (CNFETs), logic, and sensors] (D); and scanning electron microscope images of CNT circuits and devices on top of a 3D N3XT chip (E) (scale bars, 500 nm).

At the individual device level, recent studies have shown short gate lengths (10 nm), complementary p-channel and n-channel devices with near-ideal subthreshold swings for single CNT transistors, and for devices with 50 CNTs per micron The density of aligned CNTs has a high on-state current per width. In the near future, it will be possible to integrate the following elements in a single device demonstration (shown separately): gate-all-around geometry, >250nm/micron in a highly consistent array, 3nm oxide dielectric (target oxide Capacitance = 2.94 × 10?10 F m?1), sub-10-nm p-type contact resistance of 6.5 per kohm, sub-10-nm gate length, multiple stacked inter-channel layers, and doped source or drain extensions . This MOSFET-like carbon nanotube structure with 35nm contact-gate pitch and 20nm active width is expected to far outperform Si transistors in 2nm node logic technology.

3D Integration

Future semiconductor chips will move beyond the miniaturization of two-dimensional devices to be replaced by active devices with three-dimensional layers. Since 3D logic device layers must be thin and fabricated at temperatures compatible with back-end-of-line (BEOL) wiring layers (typically <400°C), CNT transistors are particularly well suited for 3D integration due to low device fabrication temperatures and thin device layers. Since the first demonstration of an all-carbon-nanotube-transistor computer about a decade ago, progress has been made not only at the level of integration, but also in device diversity, and the maturation of the technology from university laboratories to industry.

A four-layer monolithic integrated chip consisting of a silicon transistor layer, a carbon nanotube transistor memory readout circuit layer, a resistively switched metal oxide random access memory (RRAM) layer, and a carbon nanotube transistor sensor layer on top illustrates monolithic integration benefits (Fig. 5, C to E).

This 3D chip can process information in parallel at terabytes per second, from sensors to memory cells to transistors. Another example is the end-to-end brain-inspired ultra-dimensional computing nanosystem, which is very effective for cognitive tasks such as language recognition, which is realized by the monolithic 3D integration of CNT transistors and RRAM, using BEOL interlayer vias to enable computing Fine-grained and dense vertical connections between layers and storage layers. The carbon nanotube transistor fabrication process is not only shown on a full 200 mm wafer, but also has 3D integration with RRAM.

Radio Frequency Electronics

Although digital electronics remains the main focus of the field, CNT transistors also hold great promise for high-frequency radio-frequency transistors. Many of the material and device requirements for digital carbon nanotube transistors also apply to radio-frequency electronics, with a relaxed need for semiconductor purity and an increased need for high transconductance and linearity, which translates into low distortion when amplifying signals. Recent advances in radio-frequency carbon nanotube transistors made of nanotube arrays demonstrate the ability to operate at frequencies up to hundreds of gigahertz with attractive low power consumption and high versatility for on-chip integration system application.

The purification capability of the solution-phase dispersion of semiconducting CNTs also enabled printing into thin-film devices (Fig. 2H). Numerous reports have shown that fully printed CNT-TFTs can be used in digital logic circuits to illustrate the ability of these devices to provide computing functions. However, given the low cost of conventional node silicon transistor technology, the likelihood that printed CNT-TFT circuits will be widely used is low. Even more encouraging is the use of printed CNT-TFTs for backplane control of displays or for custom biosensing systems. Recent research has also revealed the recyclability of carbon nanotube films, which shows promise for fully printed paper-based electronic systems in which all core materials can be recycled and reused.

Future Development and Prospects

Material Outlook

Advances in materials are expected to be central to future advances in carbon nanotube transistors. Improving the purity of semiconducting carbon nanotubes is critical for all device use cases. In this regard, one of the biggest obstacles to reducing metallic CNT impurities to parts-per-million or part-billion concentrations is the lack of high-throughput analytical methods for the detection of ultra-low concentrations of metallic CNTs. For carbon nanotubes, most high-throughput optical detection methods (such as photoluminescence spectroscopy) are less sensitive, if not completely insensitive, to metal species. In fact, the only sure way to quantify ultra-low concentrations of metallic CNTs is to fabricate large arrays of individual CNT transistors and then electrically probe them individually to look for short circuits. This method is time-consuming and will only get worse as the purity of semiconductors increases. Therefore, most CNT separation methods are only optimized to the detection limit (99.9%) of the optical spectrum.

Another unresolved issue of semiconducting carbon nanotubes is the need for a scalable and sustainable manufacturing method to produce ultrahigh-purity semiconducting carbon nanotubes in sufficient quantities to satisfy a potentially huge market, not only including high-performance integrated circuits , also including high-volume printed electronics. There are no fundamental barriers to scalability for most solution-based separation methods, but the throughput of these processes is ultimately limited by the quality of the input feedstock. To improve the yield of downstream separations, improved synthesis processes are required to minimize impurities and maximize the purity of semiconductors with narrow nanotube diameter distributions. One tantalizing option is to refine cloning techniques to the point where iterative isolation and amplification can be achieved in a manner similar to the polymerase chain reaction (PCR) in biochemistry.

Ultimately, growth conditions encompass such a large parameter space that methods for efficiently searching and identifying optimal growth conditions are needed. Emerging artificial intelligence and machine learning optimization methods combined with high-throughput experimental screening hold promise for the next generation of integrated work. Similarly, the discovery, optimization, and integration of many other materials (including dopants, contacts, gate electrodes, and dielectrics) in CNT transistors can also be accelerated by machine learning coupled with high-throughput experimental screening.

Equipment Outlook

Although much has been learned about establishing interfaces to carbon nanotubes, including gate structures and contacts, challenges remain. The role of material selection and purification (discussed previously), fabrication methods, and doping controls continues to be elucidated in numerous reports. In fact, one of the most important challenges moving forward is determining (among the thousands of materials and processes reported) which combination is best to use. More systematic studies are needed to explore the impact of certain contact and capping material configurations on device performance, yield, reproducibility, and stability. For example, carbon nanotube channels can be extended to lengths below 10 nm in various configurations, but it is unclear which device structure is superior (e.g., top-gate vs. full-gate, side-contact vs. edge-contact), and which performs best The option also has a manufacturing process compatible with the associated fabrication in a complementary metal-oxide-semiconductor (CMOS) fab. Most formation processes with metal contacts rely on a lifting process, which is thought to be a non-scalable process, while non-lifting alternatives also tend to rely on slow patterning processes.

The scalability of the contact length requires further consideration, a parameter that is as important as scaling the gate length of the transistor as a whole. Some studies have shown severe degradation at contact lengths below 30 nm, while others have shown less degradation at corresponding lengths, but high yields have not yet been achieved. This contact length scaling challenge is common to all transistors, but discovering a solution that allows for substantial scaling of contacts without degrading the device will be a key advance. End bonding or edge contact offer one such possibility, although further work is needed to reduce processing temperatures and understand transport and performance limitations. Furthermore, the realization of equally high-quality and scalable contacted n-type CNT transistors remains to be solved.

For TFTs from carbon nanotubes, much of the knowledge gained from nanoscale field-effect transistor devices is applicable. The most important exception is that TFT technology should ideally be compatible with large substrate sizes and have very low cost. Since one of the main applications of TFTs is on display backplanes, the materials and processes should be scalable to large panels. While device-level performance and size are important, TFTs loosen the constraints and put more emphasis on manufacturing cost, as these devices will be used in commodity applications (such as backplanes) or single-use applications (such as IoT). The recent demonstration of recyclable printed carbon nanotube-TFTs on paper substrates suggests a sustainable measure. Improving the yield and stability of CNT-TFTs is crucial, especially the role of tube-tube contacts in percolation networks.

Technology Prospect

There are many remaining hurdles to realizing CNT transistor technology that meets the needs of high-volume production and will require concerted efforts from academia and industry to overcome. Regarding semiconducting carbon nanotube purity, although the highest purity is still the ideal purity for EDP, logic design techniques can be used to relax the requirements for some applications by a factor of about 100 (from 99.9999 to 99.99%) without adding additional processing steps or redundancy.

For high-performance digital systems, device variation plays an important role in determining the overall EDP and noise margin of the system. Sources of variation specific to CNTs include CNT density and pitch (distance between CNTs in multi-CNT transistors), CNT bandgap (determined by chirality and diameter), and random fixed charge on the surrounding extreme sensitivity (which is why carbon nanotubes are ultrasensitive sensors).

Transistor widths (perpendicular to the direction of current flow) for logic technology are on the order of 20 to 40 nanometers. When the CNT density is 250 CNTs per micron, there are only 5-10 CNTs in the channel; thus, variations in CNT density and CNT spacing will result in substantial changes in current drive.

Design solutions that reduce this variation are essential as part of a co-design process for technology development. For example, changes in the bandgap of carbon nanotubes are directly translated into changes in the off-state leakage current through threshold voltage and band-to-band tunneling of the drain. The band-to-band tunneling leakage varies exponentially with the bandgap and sets the minimum achievable leakage current, which is the boundary at which the state-state and non-state leakage currents are swapped by adjusting the threshold voltage. The direct source-to-drain tunneling current also depends exponentially on the bandgap and sets a limit on gate length scaling. The choice of carbon nanotube diameter (bandgap) faces the same tradeoffs as other FETs. Small bandgap CNTs have lower effective mass and higher on-state current, while large bandgap CNTs have lower tunneling off-state leakage current, and can further shrink the gate length and maintain higher operation at high speed Voltage. Given the target computing workload, the best choice must be application-dependent and must be co-designed.

Although the CNT transistor inherits all the limitations of the MOSFET (electrostatics and transport physics) and has all the challenges of low-dimensional channel materials (contacts and surfaces without dangling bonds), it also retains all the advantages of the FET, including good Circuit or system design ecosystems and mature manufacturing technologies have further potential in increasing the number of devices and connecting chips in 3D integration. These benefits are expected to eventually outweigh all constraints, as the power of presence and scalability in three dimensions cannot be underestimated. Between the opportunities for high-performance digital logic with the potential for 3D integration and the possibility of printing and even recyclable thin-film electronics, carbon nanotube transistors deserve renewed and even redoubled efforts by academic, government and industrial contributors. These molecular transistor technologies are within reach, but only if the science and engineering community can overcome the remaining challenges.

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