New UVVM features published
Espen Tallaksen
CEO EmLogic, Co-founder TechSeed & EmLogic, Director FPGA and Space (now hiring - see my posts)
UVVM is the fastest growing verification methodology in Europe, and probably even world-wide. The ESA project to extend the UVVM functionality will now very soon be completed. Some features have been published a long time ago, and now we have started publishing a lot of new features. The most important of these are:
The watchdogs; - with a simple variant just to check that your testbench is not running too long - with alot of options to extend the time. But more important - an activity watchdog that will result in a timeout if there has been no activity on any of the VVCs for a given time.
All Bitvis VVCs now come with a built_in scoreboard capability, and with new commands to support this. A great advantage for advanced testbenches.
All Bitvis VVCs now provide the intended transaction as information to the test harness, so that for instance a model (or the test sequencer) can see exactly what is being transmitted or received, and thus use that to generate the expected response.
A dedicated Error Injector VIP is provided to manipulate signals going in to the DUT in lots of different ways.
Several other features have also been added. Check out the new release - including a dedicated demo testbench.
Principal Digital Verification Engineer at Kandou S.A.
5 年I'm glad ESA is supporting this interesting methodology to increase the ability to verify complex systems. When 5 years ago I was talking about OSVVM to members of a competency center in ESTEC they were more looking into UVM, which would have been a total overkill for the space industry in Europe, especially considering the systems at hand. I'm happy to see they have eventually switched direction