This new memory technology is challenging SRAM

In the era of new non-volatile memory (NVM) technology, another variant is about to join the fray - a new version of MRAM called spin-orbit torque or SOT-MRAM. What makes this particularly interesting is that it could one day replace SRAM arrays in systems-on-chips (SoCs) and other integrated circuits.

The main advantage of SOT-MRAM technology is that it can achieve faster write speed and longer endurance. As with any new technology, there are challenges in terms of cost and complexity, and a technology that looks attractive still may not achieve mass adoption. But as research continues, some of these shortcomings may be addressed when the technology is commercialized.

"With SOT-MRAM, because it uses a different mechanism, its write performance is 10 times that of the previous generation of STT-MRAM," said Mingchi Liu, technical marketing manager for embedded memory at Synopsys. "And it will have advantages in lifetime reliability."

MRAM is one of many non-volatile memory technologies entering commercial production today. Earlier versions, called switched MRAM, have been around for a while, and the latest commercial option is Spin Transfer Torque, or STT-MRAM.

MRAM joins the ranks of other technologies that knock flash memory off its NVM base. Flash memory still offers the lowest cost per bit so far -- a hurdle for any novice -- but it has some drawbacks, such as long programming times and the need to program and erase large blocks of data at a time. The latter makes flash management more complex. It also consumes a lot of power when programming the cell, and it is difficult to embed logic.

Compared to flash, STT-MRAM promises lower power consumption and faster write times. But this requires a trade-off between speed and endurance, suggesting that different devices may be better suited to different markets, with some tuned for performance and others tuned for applications that require many write cycles.

SOT-MRAM promises to eliminate this tradeoff. "With STT, you have to give up retention or permanence," says Antaios founder and CEO Jean-Pierre Nozières. "Here you get stamina, staying power and high speed."

Of course, replacing SRAM is a tough challenge. "SRAM can be implemented on any logic chip without any additional processing steps, it is one of the fastest memories and can be energy efficient on the fly (if there is leakage)," said Marc Marc, Group Director, DDR, HBM, Flash Product Marketing Greenberg said Cadence's /storage and MIPI IP. "But it's also one of the least area efficient, and it's not stable."

SOT-MRAM should provide some regional relief and increase volatility. While it won't replace the fastest SRAMs, it may help with larger arrays using slower SRAMs.

Understanding how SOT-MRAM addresses these challenges requires a discussion of how the basic bit cell works—and more importantly, how it is programmed.

STT-MRAM

Modern MRAM devices employ so-called magnetic tunnel junctions (MTJs). It can be simplified to have three layers - a fixed or "pinned" magnetic layer, a tunnel dielectric and a free magnetic layer.

When programming the device, the magnetic field of the free layer is set to be parallel or antiparallel to the magnetic field of the pinned layer. The idea is that the pinned layer effectively filters the spin direction of the current passing through it. When that current hits another magnetic layer, more current can pass if it's in the same direction. If the direction is reversed, less current will pass.

Cells are programmed in STT-MRAM MTJs by running a high current through the MTJ. The direction determines how the free layer is programmed. Newer programs are "harder", resulting in faster access times. But it can also cause damage to cells, which can lead to wear and tear. If higher endurance is required, the write current must be lower, slowing down the process.

"The current disadvantage is that its write speed is 10 times slower than its read speed," Liu said. "It will be difficult to replace SRAM because of slow performance."

SOT-MRAM

SOT-MRAM has a different write path, with current flowing along the bottom of the MTJ (in-plane) rather than through it. This separates the programming and read paths and eliminates corruption that can occur with STT-MRAM programming. This requires a new layer, often called a strip, through which the programming current will flow.

There are two fundamental challenges to SOT technology that remain the subject of much research and development. The first deals with the need for an external magnetic field when writing. The second has to do with the size of the bit cell.

Magnetic fieldless switching

The first challenge has to do with how to set the deterministic magnetic field orientation. In the purest sense, the programming mechanism involves some random factor, and it is difficult to control the direction of the magnetic field for a given magnetic domain.

There are at least two ways to accomplish this control. One is to make an asymmetrically shaped strap, but this affects the cell area. The other is an external magnetic field, which has obvious disadvantages.

While commercial development of external-field methods has been moving forward, researchers have identified potential ways to perform so-called "field-free" switching. For those unfamiliar with materials, surface states, spin indices, the Dzyaloshinskii-Moriya effect, the Rashba effect, and other mysteries that have emerged in many papers, the emerging solutions are difficult to understand.

But researchers [1,2] found that by sandwiching the right metal with the right combination of ferroelectric or ferroelectric materials, and the right spin index relationship, the magnetic symmetry can be broken to drive the desired direction.

The general expectation seems to be that when commercial devices emerge, they will be capable of fieldless switching.

Reduce bit cell size

A more challenging problem is that while STT cells have two terminals for read and write current to share, SOT cells have three terminals because the write current has its own path. This means another select transistor. This is the default configuration, which has larger bit cells than STT. The extra transistors are the main reason for the larger size.

"SOT outperforms STT everywhere except for one very important factor - area cost," Nozières said. "Our goal is to achieve half the area of SRAM. You can do that with zero leakage and simpler peripherals because you don't need sleep and wake modes and such."

The difference between STT and SOT bit cells may not be as great as one might think. In fact, that's less than 50 percent of the growth one might intuitively assume, says Barry Hoberman, an Antaios board member and advisor.

With STT, the write path consists of a select transistor and a high resistance MTJ. In SOT, it is the selection transistor and the low resistance band. So with STT, the transistor is under pressure to reduce resistance - which means it needs to be wider.

The SOT transistor doesn't have the same stress, so it can be smaller - enough to reduce the bit-cell size variance. The exact size and current numbers remain proprietary.

Still, SOT cells are larger than STT cells, so efforts are being made to reduce this effect. Circuit techniques and more complex ideas are presented in the paper, showing a way to eliminate one of the terminals, and we'll discuss a few examples of them. At this point, these appear to be just ideas, and it's unclear whether they'll be commercialized.

A 2018 paper [3] from CEA Tech, Aix-Marseille University, Grenoble-Alpes University and CEA Leti shows two possible circuit approaches, one of which involves some leakage through the MTJ. These don't eliminate the third terminal, but they reduce the number of select transistors to 1 and 0, respectively.

Work has also been carried out by the National University of Singapore, Indian Institute of Technology and Korea University [4] to propose a way to share the write terminals of all cells in a single row, eliminating the need for each cell to have its own write terminal.

The mechanism is subtle and involves the gate material above the magnetic stack, which can accumulate or remove oxygen ions from the free layer. The presence or absence of these ions determines the polarity of spin accumulation at the band and free layer interface. In this way, each cell on the line can be programmed to its own state using current in one direction plus the gate voltage of each cell - which does not take up the area required for an access transistor.

The challenge at this point is that the migration time of these ions is very long, which affects the write access time, so for now this is conceptual. Whether it can evolve into a commercially viable mechanism for shrinking bit cells remains to be seen.

In the long run, there are other ideas. "More radical approaches go further and make SOTs smaller in size than STTs, but that will take time and hasn't really come out yet," Nozières said.

access time symmetry

Another issue is the access time for reading and writing bit cells. SOT technology changes the writing mechanism to allow fast writes without compromising endurance. "We believe we can run this thing anywhere between 3 and 10 ns," Nozières said.

But the read mechanism remains the same. So while the write time of SOT is now faster than STT, the read time has not changed.

While faster writes might sound good in principle, it's unclear whether there's value in writing faster than reading. On average, memories are read a lot more than they are written. Therefore, increasing read speed has a greater impact on overall performance than increasing write speed.

Some argue that the best arrangement is symmetrical, i.e. the same time for reading and writing. Nozières agrees: "In effect, you want the reading time to be symmetrical."

This may end up giving up some of the write speed gains from SOT technology, but the symmetry is designed to provide "good enough" write times.

Test the magnetic field

There have also been some recent announcements of test equipment supporting SOT-MRAM. The necessary development is related to the external magnetic field and the writing time. The equipment available today is more focused on development than commercial mass production, so it needs to be able to do things that may or may not be needed in a production tester.

One of these capabilities involves external magnetic fields. Today, the ability to apply the field is necessary. However, even if field-free programming becomes a commercial reality, this field will still be required for characterization and even full testing.

Like any other parameter, the magnetic properties of a given positioning unit are affected by manufacturing variations. The inherent magnetic properties of the bit cell must be measured, and this is done with an external field. In fact, testing the stability of an array in the presence of an external field means determining the coercive field—that is, how well the programmed state supports other nearby fields.

"With STT, we change the magnetic field on top of the MTJ, and then we can flip the state of the device," said Siamak Salimy, CTO and co-founder of Hprobe. "From that we extract the coercive field, and then the anisotropy field. We do the same thing with SOT, but we need a 2D magnetic field, whereas STT only needs 1D."

Nozières explained the concept of magnetic anisotropy. "This is the preferred direction of magnetization," he said. "Hopefully uniaxial, this enables two states, depending on the direction along that axis. It represents the 'stiffness' of the magnet. The coercivity is what is required to overcome the anisotropy and switch from one direction to the other The value of the magnetic field. In an ideal world, it is the same as anisotropy. However, materials have defects and the coercivity is always lower than the anisotropy, and sometimes much lower than the anisotropy.”

Therefore, testers may need to be able to apply and adjust local fields in a precise and fast manner. Accurately obtaining a known field is difficult because the field can vary from location to location—especially when using probe cards.

"The probes do some scrubbing as they touch the pads, so the contact points will vary from location to location," explained ISI President and CEO Henry Patland. "And the wafer itself isn't perfectly flat. We pair the magnets with the probes. The pin card is integrated so that during positioning of the wafer, when we touch the probe card, we are working in a uniform magnetic field."

"We typically limit ourselves to a uniform field of around 1 millimeter," said Wade Ogle, vice president and chief operating officer of ISI. "We can measure up to eight devices in parallel and still be within the uniform field."

High-speed test pulse

The analog circuitry on the test head must also be improved. Programming pulses as short as 200 ps must be generated, at least for now, because the bit cells are evaluated and refined prior to startup. This is less time than it used to be.

But there is a more difficult side function. The focus of SOT devices is the ability to program using in-plane currents rather than vertical currents. When testing and characterizing devices, you need to ensure that all programming is done through this in-plane path. The vertical path normally used for STT must be suppressed to ensure that no programming comes from any stray STT current.

"We want to maximize the switching of the device with the SOT and try to avoid current flow through the STT channel," Salimy said. "To do this, we need to apply extremely synchronized pulses to ensure that when the pulse is at the bottom of the MTJ column, we have the exact same amplitude on the other side."

Generating these types of pulses can be particularly difficult in a test environment. "We're sending 500 ps pulses through a 1-meter cable into an unterminated, high-impedance device," Patland said. The way they pulse the MTJ may seem a little different, but the idea is the same - remove any current flowing through the MTJ.

Therefore, on the test chip, the tester must be able to generate accurate pulses on both signals and synchronize them within 10 picoseconds. On commercial circuits, these pulses will be generated internally. Additionally, some technologies use "STT assist", where a small STT current supports the SOT mechanism, reducing the overall write current. But test structures for wafer acceptance testing may still require this capability.

SOT-MRAM vs. Flash and NAND

The big question is where SOT-MRAM can get attention. Based on cost alone, it or any new NVM will have a hard time competing with NAND flash or DRAM.

"While DRAM and NAND are already highly optimized and may not be able to make new advances at the same speed as new memory, they benefit from decades of technology investment by some of the world's largest semiconductor companies in a market that sells tens of billions of chips . product value per technology per year," Greenberg warned. “A lot of money has been spent optimizing DRAM and NAND to where it is today. So even if a new technology improves by 20% per year, it still has a long way to go to catch up with DRAM and NAND.”

Getting better at one or two things might help, but in general, the maturity of flash and DRAM and the fact that they continue to evolve may make dedicated MRAM chips out of economics.

"On some metrics, novel memory is not good enough to beat established memory," Greenberg added. "It has to beat DRAM on almost all key metrics such as bandwidth, latency, capacity, cost, power and endurance. or NAND."

Anteos doesn't seem to have any illusions about it. "Like today's technology, specialized chips seem out of reach because it will never be able to compete with DRAM in terms of cost."

MRAM and SRAM

However, as embedded memory, the situation is different. Both embedded flash and DRAM are difficult and require many additional processing steps. MRAM requires fewer additional steps and is largely compatible with CMOS logic processes.

Subodh Kulkarni, president and CEO of CyberOptics, said: "There are commercial chips that use MRAM to achieve their unique value proposition, albeit with greater functionality than DRAM or NAND."

From a processing standpoint, SOT doesn't need anything that STT doesn't, with one exception, so foundries running STT should also be able to run SOT. The exception to that is metal layers that may provide fieldless programming. Some believe it's close enough to known fab-friendly metals to not be a problem. But it's a new material, so it's possible that some additional qualifications are going on there.

As embedded memory, SOT may or may not directly compete with STT. "I'm pretty sure that, first of all, SOT will complement STT," Nozières said. “The manufacturing environment, materials, processes, equipment are all the same. There is nothing stopping a foundry from offering Class A and Class B MRAM to all customers.”

In this case, it is more likely to compete with SRAM. The power consumption of SOT-MRAM and SRAM is roughly equivalent. But SRAM still has an advantage in speed, so SOT-MRAM may still not be able to implement the first level cache.

"The first tier of caching puts them in the 300 ps cycle time frame," Hoberman said. "This is entirely the domain of MOS -- and it's likely to be for a long time."

The last layer of caching seems like an opportunity, and density is a benefit for this application. STT-MRAM could theoretically play a role there if the endurance can be achieved at the desired write speed. But system designers are so used to SRAM's infinite durability that even having to consider durability can be a negative. “With SRAM, no one will question its longevity,” Liu said.

The simple refresh feature of STT in exchange for lower data retention has been discussed. This might make it suitable for the last level cache, where the data lifetime is relatively short.

"If you want to replace SRAM with embedded MRAM, do you care about data retention?" Liu asked. "If it could hold a day's worth of data, would that be enough? Actually, a day is too long. Maybe just an hour is enough. And the system is completely refreshed every minute."

In this way, STT and SOT may compete with each other, as refresh complexity trades off with smaller bit cell size. Then again, if the refresh is done in an easy-to-use way and doesn't add too much to the die cost, it can be tolerated like DRAM refreshes are today.

IoT devices will be another story. “[STT with refresh] is definitely not suitable for IoT where data retention is required,” Liu points out.

They also need to reduce power as much as possible, since many of them use small batteries. "The write energy per bit of SOT is about an order of magnitude lower than that of STT," Hoberman said. Non-volatility is also an advantage, as the system state can survive power cycles. This has the potential to speed up startup times.

The significance of EDA's entry into China is still a few years away

Whether these benefits will support SRAM in some applications is unknown. SOT-MRAM development continues, but it will take some time. "I don't think the technology will be available for customer samples until 2024," Nozières said.