The Need For 3D IC Packaging And Design Evolution

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If you are familiar with Moore’s Law, you’ve probably read pronouncements that the premise of transistor counts doubling each year is reaching a wall due to complex process technologies and device physics limitations.

Regardless of how well transistor counts continue to scale, market segments continue to drive the thirst for more compute performance and fast time to markets. Artificial intelligence (AI), which has greatly impacted the computing world and its hardware processing architectures, is an example of one such segment. In order to meet the performance, memory, thermal and overall total cost of ownership requirements, design engineers are looking to specialized system solutions and custom silicon to meet their needs. These systems come in the form of ASICs, FPGAs, and/or GPUs accompanied with high bandwidth memories or chiplets in a variety of 3D packaging solutions. These packaging system solutions provide the necessary compute, IO, and memory scaling to address specialized workloads in the compute intensive markets like machine learning or AI.

Multi-die integration and 3DIC packaging is becoming an increasingly used approach to multiply integration densities and performance in a single package. It is a way to extend design scale by working around Moore’s wall. Continuing the AI market segment example, as compute core performance improves in specialized accelerators, more demand for higher memory bandwidth and the need for larger numbers of HBM dies are increasing the challenge of integrating it all in a single package. With designs containing two to four HBM dies becoming more common (Figure 1), this adds more complexity to the multi-die systems in a package. These complex heterogeneous integrations with high density die-to-die connectivity are surpassing the performance capabilities and the database size limits of traditional EDA tools for package design.

Figure 1: Multi-die system in a package with 3D stacked HBM

Advanced packaging solutions enable higher levels of integration and improve overall system performance and cost. Yet, these solutions also result in challenges (Figure 2) due to a larger form-factor, need for larger silicon interposer, higher power, increased thermal, and longer design cycles, that all must be addressed.

Figure 2: Challenges of 2.5D/3DIC Package Design

With 2.5D and 3D multi-die integration, IC packaging requirements are much more like IC design requirements on an SoC-like scale, with hundreds of thousands of inter-die interconnects. Using multiple point tools that only address sub-sections of this complex problem create large design feedback loops that do not allow convergence to an optimal solution in a timely manner. Additionally, many of these point tools lack automation, have separate user interfaces with different use models, or are supported on different platforms that make data sharing almost impossible and very time consuming to support or to enable.

All these issues can be addressed by a unified platform with tight integration of system level signal, power, and thermal analysis, delivering automated power, thermal, and noise aware optimization. Having a consolidated view of the entire system is especially important because power and thermal analysis of an individual die in isolation is no longer enough in a multi-die environment – the full system needs to be analyzed together.

3DIC Compiler from Synopsys, developed in close collaboration with key customers and foundries, is poised to enable a new era of 3DIC design. It is built on an IC design data model, enabling scalability in capacity and performance with more modern 3DIC structures. It provides a single environment with planning, architectural exploration, design, implementation, analysis, and signoff – all in one.  In addition, 3DIC Compiler sets a new standard in IC packaging usability with its unique and user-friendly visualization capabilities such as 360° 3D view, cross probing, etc. for all views (architecture, planning, design, implementation, analysis, and signoff). With 3DIC Compiler, we are providing a solution where system architects, SoC & IP designers, and package designers can work on one platform capable of driving early trade off decisions all the way to final sign-off for power, thermal and reliability.(Article is from Rita Horner)