My plaque of ESD nuggets

Most of designers in semiconductor industry would agree that ESD is a real pain in the neck. Over time many of them stop bothering about it believing that it is nothing but black magic played by ESD experts. And they start playing the game to somehow get their design and layout blessed by ESD experts and leave rest to the God. If design passes ESD test, they get sigh of relief. If design fails ESD test, then the real fun begins as debugging ESD failure is nothing less than nightmare for designers more so as responsibility of releasing the product lies with design team and not ESD experts.

Another irony is that there are ESD DRC run set, but even zero DRC error does not bring smile on the face of designers as they know that it does not guarantee escape from post silicon fire-fighting. There might be EDA tool to simulate ESD performance but I am not aware of any popular one which is used across the industry. Without robust EDA tool, struggle continues in the industry among designers and pushing ESD performance curve is a rarity over the years.

One more thing I would like to share that many designers believe that if ESD cell is 2KV compliant, then the product which uses this cell should certainly pass 2KV. I think, point is missed that ESD is a chip level issue and 2KV compliant ESD cell is necessary but not sufficient for 2KV performance at the product level.

I myself have gone through several instances of intense grinding which forced me to learn bit by bit. I have compiled all my understandings in one place and have shared with you. It goes without saying that I am certainly not claiming any authority on the subject.

ESD stands for Electrostatic Discharge. Electrostatic means “stationary” charge.

There are three ways in which electrostatic voltage is typically generated:

1. Tribo-electrification

2. Induction

3. Conduction

1. Tribo-electrification

 Two different materials come in contact. Exchange of free electrons takes place. When separated, residual charge is left. Amount of residual charge depends on difference of work functions. The excess charge generates voltage .. Value depends on capacitance of the system (V=Q/C). Energy stored depends on charge and capacitance of the system.

2. Induction

  A conductive object “B” comes close to a charged object “A”. Part of the field terminates on “B”, resulting in internal separation of charge. Momentarily grounding B removes the polarised charge. When “A” is removed from the area, a net charge exist on “B”, opposite in polarity to what existed on “A”. Grounding “B” once again balances the charge.  

3. Conduction

  One charged conductive object comes in contact with other conductive object. Charge is transferred to other object through conduction. 

Why ESD is a real threat for Semiconductor product? - A deep dive

 Electrostatic charge generation can generate voltage in the range of 100V to 10,000V in the environment. 1 nano gm =(10^-9 gm) of aluminium has got enough number of electrons to generate 30,000V on a capacitor of 100pF (1 nano gm of aluminium has got 1.88X1015 number of electrons). The energy stored is of the order of 1uJ to 10mJ. (Energy = ?*C*V2).

 Electronic component is susceptible to this kind of Voltage and energy level. Breakdown Voltages in semiconductor devices are in the range of Tens of Volts.

1uJ is good enough to raise the temperature of 1000u long, 1u wide and 1u thick metal (aluminium) line by around 400 degree c.  

Density of aluminium = 2.7g/cm3  

Volume = 1uX1uX1000u = 10-9 cm3

Mass = 2.7X10-9 g

Specific heat of aluminium = 0.897 J/gK

Heat = Specific Heat X mass X Temp rise

So Temp Rise = 1uJ/(0.897X2.7X10-9 ) = 412 degree C

Melting point of Aluminium is 675 degree C.

Melting point of Silicon is 1415 degree C, Density is 2.33g/cm3, Specific Heat is 0.7J/gK. 

Since amount of mass in semi-conductor chip is very small – of the order of nano gm, uJ of energy is good enough to raise the temperature beyond melting point of Metal and Silicon/Silicon-di-oxide.

How to mitigate the threat:

 Threat can be minimised by two approaches:

1. Minimise the environmental exposure by providing systems and safeguards to minimise charge generation and charge transfer
2. Produce robust devices through process and circuit improvements

This article would focus on the second approach

Increasing Breakdown voltages and thermal capacity in the IC is very difficult. So well known concept of “Lightning Rod” is used in the IC to minimise the impact of ESD. Lightning rod is a metal rod mounted on top of a building connected to ground through a wire to protect the building in the event of lightning strike. Lightning rod should have very low electrical resistance to allow all lightning charge to flow through itself and it should have high thermal capacity so that it is able to absorb all energy in the lightning without damaging itself.

In the context of IC, it should have additional properties. It should generate low impedance between any two points on the IC; no ground node available. It should clamp the voltage below breakdown voltages (Di-electric and junction). It should turn-on only during ESD event and speed of turn-on should be fast enough.  

The above requirements make the design for ESD robustness, very challenging. 

Industry Standards:

To design/test robustness for ANY ESD event is very difficult and inefficient as well. 

IC industry has thus standardised three basic models based on how charge is transferred during ESD event, component holding charge and discharge impedance and voltage/energy. 

HBM – Human Body model: Simulates the ESD from a person discharging to an IC pin

MM – Machine model: Simulates the ESD damage caused by equipment used in manufacturing, Charged equipment discharging through IC

CDM – Charged device model: A charged packaged part discharging to a grounded conductor

Detail of HBM:

Tester Setup:

C1=Capacitance of 100pF; Charge impedance of R1= 106 – 107 Ohm; Discharge impedance R2=1.5K 

Voltage 1000-8000V; Energy at 4000V equal to 800uJ

Typical discharge current waveform:

Tester has got its own parasitic, which would have impact on validity of test results.  Tester parasitic is verified by shorting the DUT and checking current waveform; 

Ipeak = ESDV/1.5K = 0.6A for 1000V; Tri<10ns; Tdi<150+/-20ns; Pk-Pk Ringing < 10% of Ipeak

For a given part, the actual waveform could be different from this. Most of the energy is dissipated in source resistance R1 of 1.5K. 

In HBM, ESD zap voltage (positive and negative polarity) is applied across any two pins including Power/Ground pins. 

 For 20-pin parts, total number of Zaps would be 190X2=380. To simplify this and reduce the number of Zaps, pins are divided into two categories – Supply and I/O. Each pin in turn (including supplies) is zapped with respect to Supply1. This would check individual Power clamp associated with each power supply. Each pin zapped with respect to Supply2, 3 … n. Each I/O pin zapped with respect to all other I/Os shorted together. In this way, ESD device of individual I/O pin can be checked.

Total number of Zaps = ((PX(N-1)+IO))X2, P = number of supplies, N=Total number of pins, IO=number of I/O pins=N-P

For 20-pin parts, with 1 power supply pin, total number of Zaps would be equal to 76 (much less than 380)

During each Zap, all un-zapped pins are left floating. No-connect pins are considered IO pins and zapped accordingly. 

ESD classification:

250V<V<2KV : ESD sensitive

2KV<V<4KV: ESD sensitive but not to handling

4KV<V<8KV : ESD robust (Automotive Industry Requirement)

Goal of 2KV is generally acceptable.

Machine Model:

Tester Setup:

It is similar to HBM. Difference is in Resistance, capacitance and Tester parasitic values.

Capacitance of 200pF (Twice of HBM model); Discharge Resistance = 0 ; Discharge Inductance = 0.75uH; Voltage 100-500V; Energy at 100V equal to 1 uJ

Under short circuit condition, acceptable discharge current waveform is shown below:

Current is oscillatory in nature due to inductance. Since discharge resistance is negligible, all energy is dissipated in the chip itself. Peak current is very high compared to HBM model. (6A vs 0.3A for 400V). Discharge time is lower compared to HBM. Procedure and number of zapping is similar to HBM model.

Goal of 200V is generally acceptable.

Charged Device Model:

Tester Setup: Direct Charge Method

Tester Setup: Field Induced Method

Detail:

Capacitance is decided by DUT itself .. From 10pF to 100pF. Discharge Resistance = 0. Voltage 100-2000V. Energy at 1000V for 20pF part, equal to 10 uJ.

Typical Discharge Current Waveform:

 CDM is package sensitive, as energy is a function of chip capacitance. Higher capacitance means higher energy and hence more prone to failure.  Chip is charged through field induced method; both positive and negative potential. Then chip is discharged through each pin (including power/ground pins). So if there are N-pins, then there would be 2N times zapping. Since there is very negligible resistance in the discharge path, the peak current is very high. Rise/fall time is very fast due to very low resistance/inductance in the discharge path.  

Goal of 500V is generally accepted.

Design For ESD Robustness : HBM

HBM ESD zapping is done between any two pins.  This would dictate discharge path between any two pins. One could short different pins through metals to provide discharge path. However this would interfere with normal operation of the chip.

So discharge path would require some semi-conductor switch which would turn-on during ESD event and would remain turned-off during normal operation. These switches are called ESD devices.

 To have discharge path between any two pins, one could add ESD switch between any two pins. However, this would require a huge number of switches. For 20 pin part, the number of switches required would be 20C2 = 210. 

So what is done is that for each pin an ESD switch is connected between that pin and a common node (typically GND). With this strategy, for 20 pin part, the total number of switches required would be just 20. However, in this case, there would be two switches in series in the discharge path, which is less robust compared to one switch.  

 One should be aware that there would be finite interconnect resistance between two pins. 

Multiple path for ESD current should be avoided at the pin. If there is any, ESD switch should be preferred path. The other path should have much higher resistance compared to ESD switch path. 

HBM ESD phenomena is mostly related to peripheral circuit. If designed properly, internal circuits are not damaged. 

ESD Switch:

Diode, BJT, MOSFET or SCR can be used as an ESD switch.

Desired characteristics of ESD device:

1. Trigger voltage is much higher than normal operating voltage, but less than breakdown voltage of internal device
2. Ron of the device should be optimum. Very low RON would increase the current. High RON would cause higher voltage drop
3. Should turn-on fast uniformly. – minimum internal parasitic and symmetric layout
4. Should have enough area to dissipate the energy without increasing the temperature

Diode is the simplest ESD device. 

1. We need to put two-didoes to take care of positive and negative Zaps. It may not be acceptable for some parts like I2C, where diode to VDD is not acceptable.
2. Diode works fine in forward direction. However, during negative ZAP, diode can go into reverse breakdown and diode is not a good ESD device in reverse bias. 

Details of ESD Switch:

 Protection capacities: NMOS : 16V/um, NPN BJT: 37V/um, SCR: 80V/um

In CMOS process, Grounded Gate NMOS is the most popular ESD device. True BJT and SCR are not available in CMOS process .. Parasitic devices are not so efficient . SCR is prone to latch-up

Gate is connected to “ground” to ensure negligible leakage current during normal operation. 

During positive ZAP, NMOS device SNAP back behaviour shunts the current. 

During negative ZAP, forward drain to bulk diode would shunt the current. PMOS gate/source connected to VDD can be used to shunt current during negative ZAP using SNAP back characteristics. However, it would take area. 

Diagram of grounded gate ESD device:

Vt1 is trigger Voltage, which is more than normal operating Voltage and less than breakdown voltage of the gate. Optimum Voltage would be exactly in the middle. It is around 9V for 5V process.

Vh is holding voltage. It is around 7V for 5V process. It should be higher than Maximum operating voltage. 

Vt2 and It2 are 2nd Breakdown Voltage and current. This is triggered by Thermal runway. 

It2 should be much more than Short circuit current for HBM testing. For example, for 4KV performance, it should be more than 4K/1.5K = 2.6A. For 2KV, 1.3A would be good enough. 

ESD group designs and characterises ESD cell to achieve above requirements. 

 Gate Coupled NMOS can be used to reduce Vt1 with respect to 2nd breakdown condition.

 In most cases, gate-drain overlap capacitance is good enough for the coupling. And dedicated capacitance is not added.

During ESD event, high voltage at source gets coupled to the gate. Higher gate voltage increases substrate current and hence snap-back voltage reduces.  

Higher resistance/capacitance value would increase the coupling .. However there is a limit .. After some point it starts degrading. 

Layout Consideration fro ESD Switch:

ESD current path should be identified.

Layout should be as uniform as possible to make sure that ESD current flow is uniform and there is no current crowding. 

Current crowding increases local temperature and hence thermal damage. 

All metal/Diffusion ends are rounded. 

Current entry/exit path should be checked and should be parallel.

Spacing between contact and gate in drain side is very important. Larger space increases ESD robustness. This increases the resistance in drain path and hence tries to make current uniform. Gate-Drain junction gets heated during ESD discharge. Contact away from this point helps to prevent thermal damage. 

If source and bulk are not connected locally, then spacing between Contact and gate should be increased in source side as well. 

Use Ladder structure for uniform current distribution.

Length should be minimum to reduce base width of Lateral NPN device and hence higher current gain.

Finger Length should be between 40 to 100u

7-10 fingers is good enough for 4KV. It is to be noted that bigger width increases Pad capacitance.

Use multiple minimum sized contacts. Contacts should be properly aligned. 

Bulk/Substrate connections are in ring. Double Guard rings inside Nwell (P+ to gnd, N+ to VDD) and outside NWELL (Nwell/N+ to VDD and P+ to GND) are must.

Use straight lines as much as possible. Turn should be smooth (45degree). 

      ESD resistor: 

 ESD resistor is the resistor between ESD device and the internal circuitry. This is added at the Input pin. 

The value of this resistor should be as high (in the range of 500 ohm to 1K) as possible without effecting normal performance of the chip. 

This resistor is added to isolate internal circuitry from the ESD device. 

Diffusion resistor has got better thermal and electro-migration behaviour. However, it has got low resistivity and hence occupies more area.

ESD resistor can not be placed at the output pin and in power clamp as it would effect normal performance. 

Secondary ESD protection:

This is placed in the input pad, close to the input circuitry. 

This turns-on in the beginning of Zapping to shunt the current, if primary device takes longer to turn on.

 This is basically second level of defence.

 This is again grounded gate NMOS. Device size is much smaller compared to primary device.

This device helps in fiCDM as well in some cases.  

ESD protection for Output pin:

 For CMOS output, output driver itself can be used for ESD protection. 

 All layout related consideration from ESD point of view, should be taken into account in NMOS/PMOS output driver.

If driver size requirement is smaller than ESD requirement, then remaining devices should be turned-off by connecting their gates to VDD/GND through some resistor.

Power Clamp:

ESD device connected between Power Supplies is called Power Clamp. 

In case of multiple Power Supplies, one should identify the set of power supplies which are going to circuit and ESD device is needed to protect them.

For example, if there are two VDDs (VDD1, VDD2) and two Grounds (GND1, GND2) and there is no circuit between VDD1 and GND2. Then it may not be needed to put a power clamp between VDD1 and GND2.

If there are two Supply PADs which are connected to same pin, but they are not connected in metal on chip, then they should be treated as two separate power supplies.

Back to back diodes are added between two grounds as power clamp. 

Generally, power clamp is not added between two VDDs . ESD current flows between VDD1 to GND and then GND to VDD2, when zapping is done between VDD1 and VDD2.  

If area permits, multiple Power Clamp distributed across the chip is going to improve ESD robustness. 

Structure of Power Clamp:

 Since there is no resistance between power clamp and internal circuit, internal circuit is susceptible to ESD zapping involving power supply pins. Here gate oxide is not susceptible but source to bulk diode junction capacitance is on the line of fire. Junction capacitance breakdown voltage is higher, nevertheless generally it requires protection.

That is why it is very important to turn on Power Clamp as quickly as possible. Timer circuit is added in power clamp to turn-on Power Clamp quickly.  One kind of timer circuit is shown here. 

No gate in the circuit should be connected directly to power supply or ground. One resistor should be added in the path.

All ESD structures at one place:

  Diffusion Connected to Pad:

 There should not be any diffusion directly connected to PAD other than diffusion in ESD device.

There should be Resistance between PAD and any diffusion other than ESD device. The value of resistance should be as high as possible. 

 The resistance is required to ensure that ESD current does not flow into any device other than ESD. 

 Gate connect to Power Supply:

  No Gate should be connected to Power supply (VDD or Ground) directly. There should be some resistance between them. 

This is to ensure that when ESD Zap is done between Power Supplies then gate is not damaged due to high Voltage. 

There is no such choice for Source/Drain. Because any resistance in source/drain would impact the normal performance of the part. It is assumed that Power Clamp would turn on before the current goes through internal circuits. 

Any big device, size similar to ESD device (say 300u) is prone to ESD damage. Preferably layout of such device should be done in a manner similar to ESD

Bus Resistance in ESD current path:

Even if ESD device passes stand alone, there is a good probability that part may fail. 

This is mainly because of improper hook-up of ESD device at the top level.

One should again look at ESD current path and make sure that 

• Bus width is uniform.
• Bus width is as high as possible (generally 25u is recommended) 
• There is no sharp turn in the bus
• Bus resistance is small. For 4KV, current is 5K/1.5K = 3.3A. If we assume gate breakdown voltage of 7V, then bus resistance should be less than 2ohm.

One could check the ESD current path and depending on ESD current and breakdown voltages, one could decide the requirement of minimum resistance. 

Making a ring of Bus, reduces the resistance by half. It could be connected to seal ring as well to reduce the resistance. 

fiCDM issue in Cross Domain connection:

Whenever there is connection between two power supply domain, one should be be careful about fiCDM issue. In fiCDM whole chip is charged hence VDD1 node deep inside the chip near the cross domain connection also gets charged and suppose pin VDD2 is connected to real ground to discharge the chip. Ideally path shown by blue line should have been taken (VDD1 - VSS1 - VSS32 to VDD2) and there would have been no issue. But instead, ESD current might take the route shown by red line. In which case, the gate of M3 might get damaged due to high voltage on VDD1 line.

Cross Domain connection: Potential Fixes

Local clamp MPL and MNL could be placed near to and across the receiver gates. These diodes would self discharge the respective gate voltage through the loop formed by clamp, gate and power supply node.

If speed is not an issue then resistor Rp can be placed in the signal path crossing the domain. This would increase resistance in unintended ESD current path shown by red line and push it in the intended path shown by blue line.

Charge Transfer during fiCDM test:

CGP_FP = 8-12pF; CDUT=0.3pF to 150pF 

As diagram shows, CGP_FP is first charged through very big resistor 1Gohm and then switch in path of die-ground is connected to ground plane. The 1Gohm resistor isolates CGP_FP capacitor and Voltage source Vcdm (infinite source of charge). Hence there is limited charge needs to be discharged through DUT. The charge is decided by Vcdm and CGP_FP.

Let us assume C1=CGP_FP C2=CDUT.

C1 is charged to say voltage V and connected to uncharged capacitor C2.

Energy Stored in C1 = (1/2)CV2

After connection, new voltage V= V1(C1/(C1+C2))

If C2 << C1,the V~V1 and hence there is no charge transfer

If C2>> C1, then V~0,  In this case entire charge is transferred from C1 to C2 and there is huge energy loss as well.

The energy is dissipated in finite resistor element in interconnecting wire. In this case, there is possibility that interconnecting wire would get burnt out.

If CDUT is far less than 8pF, then fiCDM performance could be very good.

As CDUT increase, it becomes more vulnerable to fiCDM test.

The metal lines which are big would have bigger capacitance to field plate and hence discharge current would flow in those lines. These lines are generally Power/Gnd line.

The value of discharge current is in the range of 7.5A for 4pF DUT capacitance. 

Hence, resistance parasitic in VDD/GND lines would drop high voltage. If gate oxide is not protected locally then it would cause damage. 

fiCDM issue in the same voltage domain:

 Even in same voltage domain, if resistance in VDD/ GND line is high, then the gate should be protected locally. 

Antenna error would give an indication of these issues.

It would be better to add diode to fix antenna error. 

How to debug ESD failure:

• Failure could be due to multiple zapping, so fresh sample testing could be done to see whether failure goes away. In fresh sample testing, more number of parts are used and one part is not subjected to all zapping. If part passes ESD requirement in fresh sample testing, then it would be considered pass. 
• If IDD is fine, but there is functionality failure, then part could be baked for 24 hours to check whether failure goes away. If failure goes away, then there is apparently no physical damage. Failure had happened due to charge injection into oxide. This could be caused due to high resistance in the ESD current path.
• Zapping could be divided into three categories (Between Supplies, Supplies and I/O and I/O to I/O). Once we know that then we could isolate whether positive or negative zap is causing the issue. This would help to find the ESD current path and the root cause.
•  If there is failure in Current, then hot spot analysis could help to identify the site of failure. 

Location of typical fiCDM Gate oxide damage:

SEM image of silicon:

Location of typical HBM contact spiking and junction damage:

SEM Image of silicon:

I would like to express gratitude to my fellow engineers and ESD experts in my previous organisations particularly ADI for their contributions in my learnings.