My evaluation of DVT Eclipse IDE for SV & VHDL Designs
My evaluation of DVT Eclipse IDE for SV & VHDL Designs
What I loved about AMIQ EDA's DVT Eclipse IDE is that 1) it is a well thought-out, mature set of integrated tools for creating SystemVerilog and VHDLdesigns and verification environments (particularly UVM) such that the project is correct by construction; 2) is supported by an in-depth structural and UML view of the architecture (including UVM and classes); 3) is supported by a smart editor that understand the structure of the language and the structure of the design, thus providing features such as smart templates, auto-complete with list of potential objects; the editor can beautify code and declutter the view of code by hiding bodies of structures that are irrelevant to debugging (e.g., modules, functions, always, tasks, etc); ease of global rename changes (e,g., signal / function / module) using refactoring; 4) automatically compiles code on the fly to detect coding errors; 4) automatically generates html documentation about all information needed for the design (e.g., modules, interfaces, assertions, classes, macros, packages, covergoups); 5) provides a smart SV linting including compliance to UVM best-use rules, and statistics about usage of sequences, assertions, coverage, and messaging).
I strongly view DVT Eclipse IDE as an essential element in the design and verification of complex designs; it is a well-integrated tool that not only allows correct-by-construction code per standard guidelines but provides users a very deep understanding of the design to facilitate debugging and communication.
Ben Cohen
Disclosure: My evaluation is impartial, and I receive no benefits of any kind in writing it. My evaluation is based on the product and my years of experience in the field of design and verification of chips.
Have you looked at FOSS sveditor? It's Eclipse IDE for SV.
Agree with this fully. Are there any other options vs. Amiq?
ASIC Engineer at Cisco
7 年Ben, I totally agree with you. I was just saying that the cost can be a big issue and a surprise for people used to Eclipse.
Book author on SystemVerilog Assertions, Verilog/VHDL/design & verification processes
7 年Tools (such as simulators, synthesizers, and editors, etc) provide productivity and companies are willing to pay a price that bears the tool worthiness. Prices are always negotiable and are based on many factors. Since I am now not in the working environment, I use for trivial code SV editor, based on Eclipse; it's free. I also used for years Emacs. However, I can unequivocally state that DVT Eclipse is by far, orders of magnitude, more productive than the free tools, particularly if you have to deeply dig into the very complex design and verification with UVM. There is a price for intellectual property and for productivity. BTW, good productive engineers also get good salaries and raises.
ASIC Engineer at Cisco
7 年Thanks for the eval. emacs/verilog-mode/various-minor-modes is great but getting stretched to its limits. However, I think you need to mention that this Eclipse plug-in isn't free, and, in fact, pretty expensive!