Multipatterning Reduction with Gridded Cuts and Vias

Even with the emergence of EUV lithography, multi-patterning has remained a necessity going into the 3nm and 2nm nodes [1]. In particular, the via layers and cut patterns tend to increase the amount of multipatterning dramatically; 0.33NA EUV quadruple patterning would be expected for a minimum CD ~10 nm [2]. For this reason, it would be important to seek out ways to streamline the multipatterning process.

Gridded Fully Self-Aligned Vias Patterned with Two Masks

A fully self-aligned via's placement is restricted by both the interconnects below and above, so that the via is exactly where it needs to be to connect the two interconnect layers [3]. Specifically, an extra dielectric barrier layer over recessed lower metal provides the extra alignment to the lower metal trench [4], while the upper metal trench pattern confines the via connection from above [3,4]. This allows the actual via mask pattern to be significantly larger than the final via connection width, which can ease patterning constraints.

Next, we can recognize that vias will be located at certain intersection points between two metal layers, which can form a grid [5]. We expect the via locations to be two metal pitches apart in either direction; these locations can be first accessed by diagonal trenches defined by SADP (self-aligned double patterning) for 40-60 nm pitches (Figure 1). Alternatively, directed self-assembly (DSA) may be used instead [6].

Figure 1. Via locations on a grid defined by the lower metal layer, upper metal layer, and diagonals (formed by SADP in this case).

The vias which need to be patterned can be "selected" by a selection mask in conventional lithography (Figure 2). DUV resolution should be sufficient, as the selection width would be several tens of nanometers. Thus, gridded fully self-aligned vias need only two masks (diagonal grid identification mask + selection mask) to be exposed with DUV lithography.

Figure 2. Via locations selected by a selection mask which only allows certain grid locations to be exposed to further processing.

Gridded Cuts Patterned with Three Masks

Cuts have been used in extra lithography steps due to the inability of tip-to-tip spaces to match the half-pitch [7]. However, the cuts themselves need to be constrained so as to not affect yield due to overlay. This is difficult to do due to the roundness of the cut patterns, even in the well-known SALELE (self-aligned litho-etch litho-etch) process [8] (Figure 3). The roundness leads to the formation of potential dielectric breakdown points where the electric field between line end tips is greatest [9]. Using spacers [10,11] avoids this issue, but the inclined line edges make via connections more resistive (Figure 4). There is also dependence of the line segment length on the overlay. Therefore, we need to continue to seek alternatives.

Figure 3. Roundness of shapes can be problematic for cutting lines due to the existence of maximum electric fields which can cause dielectric breakdown.

Figure 4. Cut shapes from spacers are safer but segment lengths are sensitive to overlay and via contact areas are impacted.

A gridded approach [12] can be applied to the cuts just as for the vias previously. The difference is there would be an extra step to define cuts using straight lines perpendicular to the metal lines to be cut (Figure 5). These cut lines are expected to match the pitch of the intercepting metal layer above, in anticipation of the potential connecting self-aligned via locations. Again, only a single DUV mask would be needed for this step, along with SADP, SAQP (self-aligned quadruple patterning), or DSA.

Figure 5. Gridded cut multipatterning is similar to gridded fully self-aligned via multipatterning, with cut lines (blue) first defined. The diagonal etch mask allows portions of these lines to be removed, and a final selection mask retains only those locations which will block the metal trench etch.

The clearest benefits of this gridded cut approach are the straightness of the cut and the reduced sensitivity to overlay; the only overlay necessary to consider is the positioning of the cut lines along the direction of the metal lines to be cut, provided the diagonal widths are sufficiently large.

References

[1] W. Gao et al., Proc. SPIE 12052, 120520G (2022); W. Gao et al., Proc. SPIE 11323, 113231L (2020).

[2] X. Su et al., Proc. SPIE 11614, 116140P (2021).

[3] https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/iedm5

[4] J-H. Franke et al., Proc. SPIE 10145, 1014529 (2017).

[5] P. Woltgens et al., Proc. SPIE 12051, 120510I (2022).

[6] M. Kamon et al., J. Micro/Nanolith. MEMS MOEMS 15, 031605 (2016).

[7] https://www.dhirubhai.net/pulse/how-line-cuts-became-necessarily-separate-steps-lithography-chen/; https://semiwiki.com/lithography/293666-how-line-cuts-became-necessarily-separate-steps-in-lithography/

[8] Y. Drissi et al., Proc. SPIE 10962, 109620V (2019).

[9] W. Gao et al., J. Micro/Nanolith. MEMS MOEMS 15, 013505 (2016).

[10] US Patent 9818641.

[11] https://www.dhirubhai.net/pulse/beol-mask-reduction-using-spacer-defined-vias-cuts-frederick-chen-zxdhc/; https://semiwiki.com/lithography/338571-beol-mask-reduction-using-spacer-defined-vias-and-cuts/

[12] M. C. Smayling et al., Proc. SPIE 8683, 868305 (2013).